6ab5ed3b66
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
111 lines
3.3 KiB
Plaintext
111 lines
3.3 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#if MAINBOARD_HAS_SPEAKER
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#define IO61_HID "PNP0800" /* AT style speaker */
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#else
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#define IO61_HID "PNP0C02" /* reserved resource */
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#endif
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/* 0:14.3 - LPC */
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Device(LPCB) {
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Name(_ADR, 0x00140003)
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/* Method(_INI) {
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* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
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} */ /* End Method(_SB.SBRDG._INI) */
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OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
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Field(CFG,DWordAcc,NoLock,Preserve){
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Offset(0xA0),
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BAR,32} // SPI Controller Base Address Register (Index 0xA0)
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Device(LDRC) // LPC device: Resource consumption
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{
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Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
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Name (CRS, ResourceTemplate () // Current Motherboard resources
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{
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Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
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0x00000000, // Address Base
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0x00000000, // Address Length
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BAR0 // Descriptor Name
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)
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})
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Method(_CRS,0,Serialized)
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{
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CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
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CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
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Store(BAR,SPIB) // SPI base address mapped
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Store(0x1000,SPIL) // 4k space mapped
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Return(CRS)
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}
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}
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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Name(_CRS, ResourceTemplate() {
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IRQNoFlags(){8}
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IO(Decode16,0x0070, 0x0070, 0, 2)
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})
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} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
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Device(TMR) { /* Timer */
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Name(_HID,EISAID("PNP0100")) /* System Timer */
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Name(_CRS, ResourceTemplate() {
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IRQNoFlags(){0}
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IO(Decode16, 0x0040, 0x0040, 0, 4)
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})
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} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
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Device(SPKR) { /* Speaker */
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Name(_HID,EISAID(IO61_HID))
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x0061, 0x0061, 0, 1)
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})
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} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
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Device(PIC) {
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Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
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Name(_CRS, ResourceTemplate() {
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IRQNoFlags(){2}
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IO(Decode16,0x0020, 0x0020, 0, 2)
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IO(Decode16,0x00a0, 0x00a0, 0, 2)
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})
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} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
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Device(MAD) { /* 8257 DMA */
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Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
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Name(_CRS, ResourceTemplate() {
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DMA(Compatibility,BusMaster,Transfer8){4}
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IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
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IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
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IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
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IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
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IO(Decode16, 0x008f, 0x008f, 0x01, 0x01)
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IO(Decode16, 0x00c0, 0x00c0, 0x10, 0x20)
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}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
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} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
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Device(COPR) {
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Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x00f0, 0x00f0, 0, 0x10)
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IRQNoFlags(){13}
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})
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} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
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} /* end LPCB */
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