6aca7e6bec
Move the DMI initialization code to northbridge folder. Leave southbridge specific settings in bd82x6x folder and call it from northbridge code. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
271 lines
7.4 KiB
C
271 lines
7.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <arch/cbfs.h>
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#include <ip_checksum.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <southbridge/intel/common/rcba.h>
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#include <console/console.h>
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/* For DMI bar. */
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include "pch.h"
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#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
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static void
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wait_iobp(void)
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{
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while (RCBA8(IOBPS) & 1)
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; // implement timeout?
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}
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static u32
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read_iobp(u32 address)
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{
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volatile u32 tmp;
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u32 ret;
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RCBA32(IOBPIRI) = address;
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RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600;
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wait_iobp();
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ret = RCBA32(IOBPD);
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wait_iobp();
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tmp = RCBA8(IOBPS); // call wait_iobp() instead here?
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return ret;
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}
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static void
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write_iobp(u32 address, u32 val)
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{
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volatile u32 tmp;
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/* this function was probably pch_iobp_update with the andvalue
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* being 0. So either the IOBP read can be removed or this function
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* and the pch_iobp_update function in ramstage could be merged */
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read_iobp(address);
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RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600;
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wait_iobp();
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RCBA32(IOBPD) = val;
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wait_iobp();
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RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600;
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tmp = RCBA8(IOBPS); // call wait_iobp() instead here?
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}
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void early_pch_init_native_dmi_pre(void)
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{
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/* Link Capabilities Register */
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RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) |
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(3 << 10) | // L0s and L1 entry supported
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(2 << 12) | // L0s 128 ns to less than 256 ns
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(2 << 15); // L1 2 us to less than 4 us
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RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16);
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RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2;
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}
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void early_pch_init_native_dmi_post(void)
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{
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volatile u32 tmp;
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tmp = RCBA32(0x0050); // !!! = 0x01200654
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RCBA32(0x0050) = 0x01200654;
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tmp = RCBA32(0x0050); // !!! = 0x01200654
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RCBA32(0x0050) = 0x012a0654;
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tmp = RCBA32(0x0050); // !!! = 0x012a0654
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tmp = RCBA8(0x1114); // !!! = 0x00
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RCBA8(0x1114) = 0x05;
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/*
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* Virtual Channel resources must match settings in DMIBAR!
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*
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* Some of the following settings are taken from
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* "Intel Core i5-600, i3-500 Desktop Processor Series and Intel
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* Pentium Desktop Processor 6000 Series Vol. 2" datasheet and
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* serialice traces.
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*/
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/* Virtual Channel 0 Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC0 and TC3 and TC4 to VC0.
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*/
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RCBA32(0x2014) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
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/* Virtual Channel 1 Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC1 and TC5 to VC1.
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*/
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RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1);
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/* Read back register */
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tmp = RCBA32(0x2020);
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/* Virtual Channel private Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC2 and TC6 to VCp.
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*/
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RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1);
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/* Read back register */
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tmp = RCBA32(0x2030);
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/* Virtual Channel ME Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC7 to VCm.
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*/
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RCBA32(0x2040) = (1 << 31) | (7 << 24) | (0x40 << 1);
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/* Lock Virtual Channel Resource control register. */
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RCBA32(0x0050) |= 0x80000000;
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/* Read back register */
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tmp = RCBA32(0x0050);
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/* Wait for virtual channels negotiation pending */
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while (RCBA16(0x201a) & VCNEGPND)
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;
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while (RCBA16(0x2026) & VCNEGPND)
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;
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while (RCBA16(0x2036) & VCNEGPND)
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;
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while (RCBA16(0x2046) & VCNEGPND)
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;
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}
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void
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early_pch_init_native (void)
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{
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volatile u32 tmp;
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pci_write_config8 (SOUTHBRIDGE, 0xa6,
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pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
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RCBA32(0x2088) = 0x00109000;
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tmp = RCBA32(0x20ac); // !!! = 0x00000000
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RCBA32(0x20ac) = 0x40000000;
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RCBA32(0x100c) = 0x01110000;
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RCBA8(0x2340) = 0x1b;
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tmp = RCBA32(0x2314); // !!! = 0x0a080000
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RCBA32(0x2314) = 0x0a280000;
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tmp = RCBA32(0x2310); // !!! = 0xc809605b
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RCBA32(0x2310) = 0xa809605b;
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RCBA32(0x2324) = 0x00854c74;
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tmp = RCBA8(0x0400); // !!! = 0x00
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tmp = RCBA32(0x2310); // !!! = 0xa809605b
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RCBA32(0x2310) = 0xa809605b;
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tmp = RCBA32(0x2310); // !!! = 0xa809605b
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RCBA32(0x2310) = 0xa809605b;
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write_iobp(0xea007f62, 0x00590133);
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write_iobp(0xec007f62, 0x00590133);
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write_iobp(0xec007f64, 0x59555588);
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write_iobp(0xea0040b9, 0x0001051c);
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write_iobp(0xeb0040a1, 0x800084ff);
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write_iobp(0xec0040a1, 0x800084ff);
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write_iobp(0xea004001, 0x00008400);
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write_iobp(0xeb004002, 0x40201758);
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write_iobp(0xec004002, 0x40201758);
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write_iobp(0xea004002, 0x00601758);
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write_iobp(0xea0040a1, 0x810084ff);
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write_iobp(0xeb0040b1, 0x0001c598);
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write_iobp(0xec0040b1, 0x0001c598);
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write_iobp(0xeb0040b6, 0x0001c598);
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write_iobp(0xea0000a9, 0x80ff969f);
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write_iobp(0xea0001a9, 0x80ff969f);
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write_iobp(0xeb0040b2, 0x0001c396);
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write_iobp(0xeb0040b3, 0x0001c396);
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write_iobp(0xec0040b2, 0x0001c396);
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write_iobp(0xea0001a9, 0x80ff94ff);
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write_iobp(SATA_IOBP_SP0G3IR, 0x0088037f);
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write_iobp(0xea0000a9, 0x80ff94ff);
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write_iobp(SATA_IOBP_SP1G3IR, 0x0088037f);
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write_iobp(0xea007f05, 0x00010642);
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write_iobp(0xea0040b7, 0x0001c91c);
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write_iobp(0xea0040b8, 0x0001c91c);
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write_iobp(0xeb0040a1, 0x820084ff);
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write_iobp(0xec0040a1, 0x820084ff);
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write_iobp(0xea007f0a, 0xc2480000);
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write_iobp(0xec00404d, 0x1ff177f);
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write_iobp(0xec000084, 0x5a600000);
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write_iobp(0xec000184, 0x5a600000);
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write_iobp(0xec000284, 0x5a600000);
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write_iobp(0xec000384, 0x5a600000);
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write_iobp(0xec000094, 0x000f0501);
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write_iobp(0xec000194, 0x000f0501);
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write_iobp(0xec000294, 0x000f0501);
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write_iobp(0xec000394, 0x000f0501);
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write_iobp(0xec000096, 0x00000001);
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write_iobp(0xec000196, 0x00000001);
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write_iobp(0xec000296, 0x00000001);
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write_iobp(0xec000396, 0x00000001);
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write_iobp(0xec000001, 0x00008c08);
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write_iobp(0xec000101, 0x00008c08);
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write_iobp(0xec000201, 0x00008c08);
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write_iobp(0xec000301, 0x00008c08);
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write_iobp(0xec0040b5, 0x0001c518);
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write_iobp(0xec000087, 0x06077597);
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write_iobp(0xec000187, 0x06077597);
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write_iobp(0xec000287, 0x06077597);
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write_iobp(0xec000387, 0x06077597);
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write_iobp(0xea000050, 0x00bb0157);
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write_iobp(0xea000150, 0x00bb0157);
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write_iobp(0xec007f60, 0x77777d77);
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write_iobp(0xea00008d, 0x01320000);
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write_iobp(0xea00018d, 0x01320000);
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write_iobp(0xec0007b2, 0x04514b5e);
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write_iobp(0xec00078c, 0x40000200);
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write_iobp(0xec000780, 0x02000020);
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}
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static void pch_enable_bars(void)
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{
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pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
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pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
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/* Enable GPIO functionality. */
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pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
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}
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static void pch_generic_setup(void)
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{
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RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
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write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */
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}
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void early_pch_init(void)
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{
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pch_enable_lpc();
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pch_enable_bars();
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pch_generic_setup();
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setup_pch_gpios(&mainboard_gpio_map);
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}
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