d13bd05b7a
Change-Id: Ib470523200929868280f57bb0cc82b038d2fedf6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <device/pci_ops.h>
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include "e7505.h"
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void *cbmem_top_chipset(void)
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{
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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uintptr_t tolm;
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/* This is at 128 MiB boundary. */
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tolm = pci_read_config16(mch, TOLM) >> 11;
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tolm <<= 27;
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return (void *)tolm;
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}
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void northbridge_write_smram(u8 smram);
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void northbridge_write_smram(u8 smram)
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{
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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pci_write_config8(mch, SMRAMC, smram);
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/*
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* Choose to NOT set ROM as WP cacheable here.
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* Timestamps indicate the CPU this northbridge code is
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* connected to, performs better for memcpy() and un-lzma
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* operations when source is left as UC.
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*/
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pcf->skip_common_mtrr = 1;
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache CBMEM region as WB. */
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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}
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