6be1a8bf08
These tables are not referenced anywhere, thus all comments about adjustments are void. Also drop stub AgesaReadSpd that is all commented out. Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
338 lines
14 KiB
C
338 lines
14 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* @file
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*
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* AMD User options selection for a Brazos platform solution system
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*
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* This file is placed in the user's platform directory and contains the
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* build option selections desired for that platform.
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*
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* For Information about this file, see @ref platforminstall.
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*
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*/
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#include <stdlib.h>
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#include <vendorcode/amd/agesa/f14/AGESA.h>
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/* Include the files that instantiate the configuration definitions. */
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#include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h>
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#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h>
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#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h>
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#include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h>
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#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
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/* AGESA nonesense: the next two headers depend on heapManager.h */
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#include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h>
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#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h>
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/* These tables are optional and may be used to adjust memory timing settings */
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#include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h>
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#include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h>
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#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
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/* Select the cpu family. */
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#define INSTALL_FAMILY_10_SUPPORT FALSE
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#define INSTALL_FAMILY_12_SUPPORT FALSE
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#define INSTALL_FAMILY_14_SUPPORT TRUE
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#define INSTALL_FAMILY_15_SUPPORT FALSE
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/* Select the cpu socket type. */
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#define INSTALL_G34_SOCKET_SUPPORT FALSE
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#define INSTALL_C32_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
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#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
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#define INSTALL_FS1_SOCKET_SUPPORT FALSE
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#define INSTALL_FM1_SOCKET_SUPPORT FALSE
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#define INSTALL_FP1_SOCKET_SUPPORT FALSE
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#define INSTALL_FT1_SOCKET_SUPPORT TRUE
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#define INSTALL_AM3_SOCKET_SUPPORT FALSE
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/**
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* AGESA optional capabilities selection.
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* Uncomment and mark FALSE those features you wish to include in the build.
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* Comment out or mark TRUE those features you want to REMOVE from the build.
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*/
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#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
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#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
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#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
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#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
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#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
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#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
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//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
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#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
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#define BLDOPT_REMOVE_DQS_TRAINING FALSE
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#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
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#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
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#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
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#define BLDOPT_REMOVE_SRAT FALSE
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#define BLDOPT_REMOVE_SLIT FALSE
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#define BLDOPT_REMOVE_WHEA FALSE
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#define BLDOPT_REMOVE_DMI TRUE
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#define BLDOPT_REMOVE_HT_ASSIST TRUE
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#define BLDOPT_REMOVE_ATM_MODE TRUE
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//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
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//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
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#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
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//#define BLDOPT_REMOVE_C6_STATE TRUE
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#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
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#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
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/*
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* AGESA entry points used in this implementation.
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*/
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#define AGESA_ENTRY_INIT_RESET TRUE
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#define AGESA_ENTRY_INIT_RECOVERY FALSE
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#define AGESA_ENTRY_INIT_EARLY TRUE
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#define AGESA_ENTRY_INIT_POST TRUE
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#define AGESA_ENTRY_INIT_ENV TRUE
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#define AGESA_ENTRY_INIT_MID TRUE
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#define AGESA_ENTRY_INIT_LATE TRUE
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#define AGESA_ENTRY_INIT_S3SAVE TRUE
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#define AGESA_ENTRY_INIT_RESUME TRUE
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#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
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#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
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#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
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#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
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#define BLDCFG_VRM_CURRENT_LIMIT 24000
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//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
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#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
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#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
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#define BLDCFG_VRM_SLEW_RATE 5000
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//#define BLDCFG_VRM_NB_SLEW_RATE 5000
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//#define BLDCFG_VRM_ADDITIONAL_DELAY 0
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//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
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#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
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//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
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#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
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//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
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//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
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//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
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//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
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#define BLDCFG_PLAT_NUM_IO_APICS 3
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//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
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//#define BLDCFG_PLATFORM_C1E_OPDATA 0
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//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
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//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
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#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
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#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
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//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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//#define BLDCFG_STARTING_BUSNUM 0
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//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
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//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
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//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
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//#define BLDCFG_BUID_SWAP_LIST 0
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//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
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//#define BLDCFG_HTFABRIC_LIMITS_LIST 0
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//#define BLDCFG_HTCHAIN_LIMITS_LIST 0
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//#define BLDCFG_BUS_NUMBERS_LIST 0
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//#define BLDCFG_IGNORE_LINK_LIST 0
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//#define BLDCFG_LINK_SKIP_REGANG_LIST 0
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//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
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//#define BLDCFG_USE_HT_ASSIST TRUE
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//#define BLDCFG_USE_ATM_MODE TRUE
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//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
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#define BLDCFG_S3_LATE_RESTORE TRUE
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//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
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//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
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//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
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//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
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//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
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//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
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#define BLDCFG_CFG_GNB_HD_AUDIO FALSE
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//#define BLDCFG_CFG_ABM_SUPPORT FALSE
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//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
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//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
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//#define BLDCFG_MEM_INIT_PSTATE 0
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//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
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#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
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#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
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//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
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//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
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#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
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#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
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#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
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#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
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#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
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#define BLDCFG_MEMORY_POWER_DOWN TRUE
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#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
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//#define BLDCFG_ONLINE_SPARE FALSE
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//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
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#define BLDCFG_BANK_SWIZZLE TRUE
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#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
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#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
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#define BLDCFG_DQS_TRAINING_CONTROL TRUE
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#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
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#define BLDCFG_USE_BURST_MODE FALSE
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#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
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//#define BLDCFG_ENABLE_ECC_FEATURE TRUE
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//#define BLDCFG_ECC_REDIRECTION FALSE
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//#define BLDCFG_SCRUB_DRAM_RATE 0
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//#define BLDCFG_SCRUB_L2_RATE 0
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//#define BLDCFG_SCRUB_L3_RATE 0
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//#define BLDCFG_SCRUB_IC_RATE 0
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//#define BLDCFG_SCRUB_DC_RATE 0
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//#define BLDCFG_ECC_SYNC_FLOOD 0
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//#define BLDCFG_ECC_SYMBOL_SIZE 0
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//#define BLDCFG_1GB_ALIGN FALSE
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#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
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#define BLDCFG_UMA_ALLOCATION_SIZE 0
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#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
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#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
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#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
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#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
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/**
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* AGESA configuration values selection.
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* Uncomment and specify the value for the configuration options
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* needed by the system.
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*/
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/* The fixed MTRR values to be set after memory initialization. */
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const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
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{ CPU_LIST_TERMINAL }
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};
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/**
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* @brief Define the RELEASE VERSION string
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*
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* The Release Version string should identify the next planned release.
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* When a branch is made in preparation for a release, the release manager
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* should change/confirm that the branch version of this file contains the
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* string matching the desired version for the release. The trunk version of
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* the file should always contain a trailing 'X'. This will make sure that a
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* development build from trunk will not be confused for a released version.
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* The release manager will need to remove the trailing 'X' and update the
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* version string as appropriate for the release. The trunk copy of this file
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* should also be updated/incremented for the next expected version, + trailing 'X'
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*/
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/*
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* This is the delivery package title, "BrazosPI"
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* This string MUST be exactly 8 characters long
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*/
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#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
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/* This is the release version number of the AGESA component
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* This string MUST be exactly 12 characters long
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*/
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#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
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/* MEMORY_BUS_SPEED */
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#define DDR400_FREQUENCY 200 /**< DDR 400 */
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#define DDR533_FREQUENCY 266 /**< DDR 533 */
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#define DDR667_FREQUENCY 333 /**< DDR 667 */
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#define DDR800_FREQUENCY 400 /**< DDR 800 */
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#define DDR1066_FREQUENCY 533 /**< DDR 1066 */
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#define DDR1333_FREQUENCY 667 /**< DDR 1333 */
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#define DDR1600_FREQUENCY 800 /**< DDR 1600 */
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#define DDR1866_FREQUENCY 933 /**< DDR 1866 */
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#define UNSUPPORTED_DDR_FREQUENCY 934 /**< Max limit of DDR frequency */
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/* QUANDRANK_TYPE*/
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#define QUADRANK_REGISTERED 0 /**< Quadrank registered DIMM */
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#define QUADRANK_UNBUFFERED 1 /**< Quadrank unbuffered DIMM */
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/* USER_MEMORY_TIMING_MODE */
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#define TIMING_MODE_AUTO 0 /**< Use best rate possible */
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#define TIMING_MODE_LIMITED 1 /**< Set user top limit */
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#define TIMING_MODE_SPECIFIC 2 /**< Set user specified speed */
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/* POWER_DOWN_MODE */
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#define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */
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#define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */
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/**
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* The following definitions specify the default values for various parameters
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* in which there are no clearly defined defaults to be used in the common
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* file. The values below are based on product and BKDG content.
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*/
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#define DFLT_SCRUB_DRAM_RATE (0)
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#define DFLT_SCRUB_L2_RATE (0)
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#define DFLT_SCRUB_L3_RATE (0)
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#define DFLT_SCRUB_IC_RATE (0)
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#define DFLT_SCRUB_DC_RATE (0)
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#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
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#define DFLT_VRM_SLEW_RATE (5000)
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/* AGESA nonsense: this header depends on the definitions above */
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/* Instantiate all solution relevant data. */
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#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>
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/**
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* @brief Customer Overides Memory Table
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*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform
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* information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...).
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* If PlatformSpecificTable is populated, AGESA will base its settings on the
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* data from the table. Otherwise, it will use its default conservative settings.
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*/
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const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
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PSO_END
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};
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