6c244bd4dd
Change-Id: I983249fb54b6fbccc4339c955cb5041848b21cf8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
83 lines
2.6 KiB
C
83 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/pnp_ops.h>
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#include "it8772f.h"
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/* NOTICE: This file is deprecated, use ite/common instead */
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void it8772f_enter_conf(pnp_devfn_t dev)
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{
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u16 port = dev >> 8;
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outb(0x87, port);
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outb(0x01, port);
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outb(0x55, port);
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outb((port == 0x4e) ? 0xaa : 0x55, port);
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}
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void it8772f_exit_conf(pnp_devfn_t dev)
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{
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pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02);
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}
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/* Set AC resume to be up to the Southbridge */
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void it8772f_ac_resume_southbridge(pnp_devfn_t dev)
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{
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it8772f_enter_conf(dev);
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pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC);
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pnp_write_config(dev, 0xf4, 0x60);
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it8772f_exit_conf(dev);
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}
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/* Configure a set of GPIOs */
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void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity,
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u8 pullup, u8 output, u8 enable)
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{
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set--; /* Set 1 is offset 0 */
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it8772f_enter_conf(dev);
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pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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if (set < 5) {
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pnp_write_config(dev, GPIO_REG_SELECT(set), select);
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pnp_write_config(dev, GPIO_REG_ENABLE(set), enable);
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pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity);
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}
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pnp_write_config(dev, GPIO_REG_OUTPUT(set), output);
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pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup);
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it8772f_exit_conf(dev);
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}
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/* Configure LED GPIOs */
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void it8772f_gpio_led(pnp_devfn_t dev,int set, u8 select, u8 polarity, u8 pullup,
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u8 output, u8 enable, u8 led_pin_map, u8 led_freq)
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{
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set--; /* Set 1 is offset 0 */
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it8772f_enter_conf(dev);
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pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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if (set < 5) {
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pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map);
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pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq);
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pnp_write_config(dev, GPIO_REG_SELECT(set), select);
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pnp_write_config(dev, GPIO_REG_ENABLE(set), enable);
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pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity);
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}
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pnp_write_config(dev, GPIO_REG_OUTPUT(set), output);
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pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup);
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it8772f_exit_conf(dev);
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}
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