6c307d7646
Run the command below to fix all occurrences.
$ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,'
Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
288 lines
7.5 KiB
C
288 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* SSD1_PWREN CPU SSD1 */
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PAD_CFG_GPO(GPP_D14, 1, PLTRST),
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/* SSD1_RESET CPU SSD1 */
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PAD_CFG_GPO(GPP_F20, 1, PLTRST),
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/* BT_RF_KILL_N */
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PAD_CFG_GPO(GPP_A13, 1, PLTRST),
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/* WLAN RST# */
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PAD_CFG_GPO(GPP_H2, 1, PLTRST),
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/* WIFI_WAKE_N */
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PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
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/* x4 PCIE slot1 PWREN */
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PAD_CFG_GPO(GPP_H17, 0, PLTRST),
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/* x4 PCIE slot 1 RESET */
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PAD_CFG_GPO(GPP_F10, 1, PLTRST),
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/* Retimer Force Power */
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PAD_CFG_GPO(GPP_E4, 0, PLTRST),
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/* PEG Slot RST# */
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PAD_CFG_GPO(GPP_B2, 1, PLTRST),
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/* M.2 SSD_2 Reset */
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PAD_CFG_GPO(GPP_H0, 1, PLTRST),
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/* CAM_STROBE */
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PAD_CFG_GPO(GPP_B18, 0, PLTRST),
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/* Audio Codec INT N */
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PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
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/* TCH PAD Power EN */
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PAD_CFG_GPO(GPP_F7, 1, PLTRST),
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/* THC1 SPI2 RST# */
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PAD_CFG_GPO(GPP_F17, 1, PLTRST),
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/* THC1_SPI2_INTB */
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PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* THC1_SPI2_INTB */
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PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
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/* EC_SLP_S0_CS_N */
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PAD_CFG_GPO(GPP_F9, 1, PLTRST),
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/* WIFI RF KILL */
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PAD_CFG_GPO(GPP_E3, 1, PLTRST),
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/* DISP_AUX_N_BIAS_GPIO */
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PAD_CFG_GPO(GPP_E23, 1, PLTRST),
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/* WWAN WAKE N*/
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PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
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/* WWAN_DISABLE_N */
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PAD_CFG_GPO(GPP_D15, 1, PLTRST),
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/* WWAN_RST# */
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PAD_CFG_GPO(GPP_F14, 1, PLTRST),
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/* WWAN_PWR_EN */
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PAD_CFG_GPO(GPP_F21, 1, DEEP),
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/* WWAN_PERST# */
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PAD_CFG_GPO(GPP_C5, 1, PLTRST),
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/* PEG_SLOT_WAKE_N */
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PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
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/* CAM CONN1 CLKEN */
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PAD_CFG_GPO(GPP_H15, 1, PLTRST),
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/* CPU SSD2 PWREN */
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PAD_CFG_GPO(GPP_C2, 1, PLTRST),
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/* CPU SSD2 RST# */
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PAD_CFG_GPO(GPP_H1, 1, PLTRST),
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/* Sata direct Power */
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PAD_CFG_GPO(GPP_B4, 1, PLTRST),
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/* M.2_PCH_SSD_PWREN */
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PAD_CFG_GPO(GPP_D16, 1, PLTRST),
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/* SRCCLK_OEB7 */
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PAD_CFG_GPO(GPP_A7, 0, PLTRST),
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/* SRCCLK_OEB6 */
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PAD_CFG_GPO(GPP_E5, 0, PLTRST),
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/* CAM1_RST */
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PAD_CFG_GPO(GPP_R5, 1, PLTRST),
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/* CAM2_RST */
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PAD_CFG_GPO(GPP_E15, 1, PLTRST),
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/* CAM1_PWR_EN */
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PAD_CFG_GPO(GPP_B23, 1, PLTRST),
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/* CAM2_PWR_EN */
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PAD_CFG_GPO(GPP_E16, 1, PLTRST),
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/* M.2_SSD_PDET_R */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* THC0 SPI1 CLK */
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
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/* THC0 SPI1 IO 1 */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2),
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/* THC0 SPI1 IO 2 */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
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/* THC0 SPI IO 3 */
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PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
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/* THC1 SPI1 RSTB */
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PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2),
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/* UART_RX(1) */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* UART_RX(2) */
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* UART_RX(4) */
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PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
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/* UART_RX(5) */
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PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1),
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/* UART_RX(6) */
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PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1),
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/* UART_TX(1) */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* UART_TX(2) */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* UART_TX(4) */
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PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1),
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/* UART_TX(5) */
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PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1),
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/* UART_TX(6) */
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PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1),
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/* UART_RTS(1) */
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PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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/* UART_RTS(2) */
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PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
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/* UART_RTS(4) */
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PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
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/* UART_RTS(5) */
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PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1),
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/* UART_RTS(6) */
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PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1),
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/* UART_CTS(1) */
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PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
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/* UART_CTS(2) */
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PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
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/* UART_CTS(4) */
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PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
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/* UART_CTS(5) */
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PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1),
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/* UART_CTS(6) */
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PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1),
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/* SPI_MOSI(1) */
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PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
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/* SPI_MOSI(2) */
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PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
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/* SPI_MIS0(1) */
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PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
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/* SPI_MIS0(2) */
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PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
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/* SPI_CLK(1) */
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PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
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/* SPI_CLK(2) */
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
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/* SPI_CS(0, 1) */
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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/* SPI_CS(1, 0) */
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PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* SPI_CS(2, 0) */
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PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
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/* I2C_SCL(0) */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* I2C_SCL(1) */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* I2C_SCL(2) */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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/* I2C_SCL(3) */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/* I2C_SCL(5) */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
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/* I2C_SDA(0) */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* I2C_SDA(1) */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* I2C_SDA(2) */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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/* I2C_SDA(3) */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* I2C_SDA(5) */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
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/* I2S0_SCLK */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
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/* I2S0_SFRM */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
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/* I2S0_TXD */
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PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
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/* I2S0_RXD */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
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/* I2S2_SCLK */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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/* I2S2_SFRM */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* I2S2_TXD */
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/* I2S2_RXD */
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* I2S_MCLK1_OUT */
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* I2S_MCLK2_INOUT */
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PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
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/* SNDW1_CLK */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
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/* SNDW1_DATA */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
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/* SNDW2_CLK */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
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/* SNDW2_DATA */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
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/* SNDW3_CLK */
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PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
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/* SNDW3_DATA */
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PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
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/* SNDW4_CLK */
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
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/* SNDW4_DATA */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
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/* SMB_CLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMB_DATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* SATA DEVSLP */
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PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
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PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
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/* SATA LED pin */
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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/* USB2 OC0 pins */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* USB2 OC3 pins */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* GPIO pin for PCIE SRCCLKREQB */
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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PAD_NC(GPP_D8, NONE),
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */
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PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
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PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
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PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
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/* HPD_1 (E14) and HPD_2 (A18) pins */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* IMGCLKOUT */
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PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
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PAD_NC(GPP_H23, NONE),
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/* A21 : HDMI CRLS CTRLCLK */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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/* A22 : HDMI CRLS CTRLDATA */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
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};
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void variant_configure_gpio_pads(void)
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{
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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};
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const struct cros_gpio *variant_cros_gpios(size_t *num)
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{
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*num = ARRAY_SIZE(cros_gpios);
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return cros_gpios;
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}
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