6dadf7f482
Specify the default path to, and automatically include the FSP binaries needed to boot a board if USE_AMD_BLOBS is selected. Simplifies board configs, and matches use in previous patforms. TEST=build/boot google/skyrim Change-Id: Ic837d264327723c8dc18a60fb16e8d41fe38b44e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77625 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
533 lines
15 KiB
Plaintext
533 lines
15 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config SOC_AMD_REMBRANDT_BASE
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bool
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select ACPI_SOC_NVS
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select ADD_FSP_BINARIES if USE_AMD_BLOBS
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select ARCH_X86
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select CACHE_MRC_SETTINGS
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select DRIVERS_USB_ACPI
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select DRIVERS_USB_PCI_XHCI
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select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING
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select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING
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select FSP_COMPRESS_FSP_S_LZ4
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select GENERIC_GPIO_LIB
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select HAVE_ACPI_TABLES
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select HAVE_CF9_RESET
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select HAVE_EM100_SUPPORT
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select HAVE_FSP_GOP
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select PARALLEL_MP_AP_WORK
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select PLATFORM_USES_FSP2_0
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select PROVIDES_ROM_SHARING
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select PSP_INCLUDES_HSP
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select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK
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select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
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select RESET_VECTOR_IN_RAM
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select RTC
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK_ACP_GEN2
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select SOC_AMD_COMMON_BLOCK_ACPI
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
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select SOC_AMD_COMMON_BLOCK_ACPI_ALIB
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select SOC_AMD_COMMON_BLOCK_ACPI_CPPC
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select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
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select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
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select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
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select SOC_AMD_COMMON_BLOCK_AOAC
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select SOC_AMD_COMMON_BLOCK_APOB
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select SOC_AMD_COMMON_BLOCK_APOB_HASH
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR
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select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
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select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
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select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
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select SOC_AMD_COMMON_BLOCK_GRAPHICS
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select SOC_AMD_COMMON_BLOCK_HAS_ESPI
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select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
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select SOC_AMD_COMMON_BLOCK_I2C
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select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL
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select SOC_AMD_COMMON_BLOCK_IOMMU
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select SOC_AMD_COMMON_BLOCK_LPC
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select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
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select SOC_AMD_COMMON_BLOCK_MCAX
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select SOC_AMD_COMMON_BLOCK_NONCAR
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
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select SOC_AMD_COMMON_BLOCK_PM
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select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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select SOC_AMD_COMMON_BLOCK_RESET
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select SOC_AMD_COMMON_BLOCK_SMI
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select SOC_AMD_COMMON_BLOCK_SMM
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select SOC_AMD_COMMON_BLOCK_SMU
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_STB
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_TSC
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_XHCI
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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select SOC_AMD_COMMON_FSP_PCI
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select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
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select SSE2
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select UDK_2017_BINDING
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select USE_DDR5
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select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
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select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
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select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
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select VBOOT_MUST_REQUEST_DISPLAY if VBOOT
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select VBOOT_X86_SHA256_ACCELERATION if VBOOT
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select X86_AMD_FIXED_MTRRS
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select X86_INIT_NEED_1_SIPI
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config SOC_AMD_MENDOCINO
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bool
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select SOC_AMD_REMBRANDT_BASE
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help
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AMD Mendocino support
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config SOC_AMD_REMBRANDT
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bool
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select SOC_AMD_REMBRANDT_BASE
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help
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AMD Rembrandt support
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if SOC_AMD_REMBRANDT_BASE
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config CHIPSET_DEVICETREE
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string
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default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO
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default "soc/amd/mendocino/chipset_rembrandt.cb"
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config FSP_M_FILE
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string "FSP-M (memory init) binary path and filename"
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depends on ADD_FSP_BINARIES
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default "3rdparty/amd_blobs/mendocino/MENDOCINO_M.fd" if SOC_AMD_MENDOCINO
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help
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The path and filename of the FSP-M binary for this platform.
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config FSP_S_FILE
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string "FSP-S (silicon init) binary path and filename"
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depends on ADD_FSP_BINARIES
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default "3rdparty/amd_blobs/mendocino/MENDOCINO_S.fd" if SOC_AMD_MENDOCINO
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help
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The path and filename of the FSP-S binary for this platform.
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config EARLY_RESERVED_DRAM_BASE
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hex
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default 0x2000000
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help
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This variable defines the base address of the DRAM which is reserved
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for usage by coreboot in early stages (i.e. before ramstage is up).
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This memory gets reserved in BIOS tables to ensure that the OS does
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not use it, thus preventing corruption of OS memory in case of S3
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resume.
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config EARLYRAM_BSP_STACK_SIZE
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hex
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default 0x1000
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config PSP_APOB_DRAM_ADDRESS
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hex
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default 0x2001000
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help
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Location in DRAM where the PSP will copy the AGESA PSP Output
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Block.
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config PSP_APOB_DRAM_SIZE
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hex
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default 0x1E000
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config PSP_SHAREDMEM_BASE
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hex
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default 0x201F000 if VBOOT
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default 0x0
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help
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This variable defines the base address in DRAM memory where PSP copies
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the vboot workbuf. This is used in the linker script to have a static
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allocation for the buffer as well as for adding relevant entries in
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the BIOS directory table for the PSP.
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config PSP_SHAREDMEM_SIZE
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hex
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default 0x8000 if VBOOT
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default 0x0
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help
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Sets the maximum size for the PSP to pass the vboot workbuf and
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any logs or timestamps back to coreboot. This will be copied
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into main memory by the PSP and will be available when the x86 is
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started. The workbuf's base depends on the address of the reset
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vector.
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config PRE_X86_CBMEM_CONSOLE_SIZE
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hex
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default 0x1000
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help
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Size of the CBMEM console used in PSP verstage.
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x1600
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help
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Increase this value if preram cbmem console is getting truncated
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config CBFS_MCACHE_SIZE
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hex
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default 0x3800 if VBOOT_STARTS_BEFORE_BOOTBLOCK
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x10000
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help
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Sets the size of the bootblock stage that should be loaded in DRAM.
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This variable controls the DRAM allocation size in linker script
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for bootblock stage.
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config ROMSTAGE_ADDR
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hex
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default 0x2040000
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help
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Sets the address in DRAM where romstage should be loaded.
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config ROMSTAGE_SIZE
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hex
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default 0x80000
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help
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Sets the size of DRAM allocation for romstage in linker script.
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config FSP_M_ADDR
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hex
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default 0x20C0000
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help
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Sets the address in DRAM where FSP-M should be loaded. cbfstool
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performs relocation of FSP-M to this address.
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config FSP_M_SIZE
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hex
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default 0xC0000
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help
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Sets the size of DRAM allocation for FSP-M in linker script.
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config FSP_TEMP_RAM_SIZE
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hex
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default 0x40000
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help
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The amount of coreboot-allocated heap and stack usage by the FSP.
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config VERSTAGE_ADDR
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hex
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depends on VBOOT_SEPARATE_VERSTAGE
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default 0x2180000
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help
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Sets the address in DRAM where verstage should be loaded if running
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as a separate stage on x86.
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config VERSTAGE_SIZE
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hex
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depends on VBOOT_SEPARATE_VERSTAGE
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default 0x80000
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help
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Sets the size of DRAM allocation for verstage in linker script if
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running as a separate stage on x86.
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config ASYNC_FILE_LOADING
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bool "Loads files from SPI asynchronously"
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select COOP_MULTITASKING
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select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
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select CBFS_PRELOAD
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help
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When enabled, the platform will use the LPC SPI DMA controller to
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asynchronously load contents from the SPI ROM. This will improve
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boot time because the CPUs can be performing useful work while the
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SPI contents are being preloaded.
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config CBFS_CACHE_SIZE
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hex
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default 0x40000 if CBFS_PRELOAD || SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
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config RO_REGION_ONLY
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string
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depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
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default "apu/amdfw"
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xF8000000
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config ECAM_MMCONF_BUS_NUMBER
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default 64
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config MAX_CPUS
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int
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default 8 if SOC_AMD_MENDOCINO
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default 16
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help
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Maximum number of threads the platform can have.
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config VGA_BIOS_ID
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string
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default "1002,1506" if SOC_AMD_MENDOCINO
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help
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The default VGA BIOS PCI vendor/device ID of the GPU and VBIOS.
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config VGA_BIOS_FILE
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string
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default "3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin" if SOC_AMD_MENDOCINO
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
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hex
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default 0xfedc9000 if UART_FOR_CONSOLE = 0
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default 0xfedca000 if UART_FOR_CONSOLE = 1
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default 0xfedce000 if UART_FOR_CONSOLE = 2
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default 0xfedcf000 if UART_FOR_CONSOLE = 3
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default 0xfedd1000 if UART_FOR_CONSOLE = 4
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config SMM_TSEG_SIZE
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hex
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default 0x800000 if HAVE_SMI_HANDLER
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default 0x0
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config SMM_RESERVED_SIZE
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hex
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default 0x180000
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x800
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config ACPI_BERT
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bool "Build ACPI BERT Table"
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default y
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depends on HAVE_ACPI_TABLES
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help
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Report Machine Check errors identified in POST to the OS in an
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ACPI Boot Error Record Table.
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config ACPI_BERT_SIZE
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hex
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default 0x4000 if ACPI_BERT
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default 0x0
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help
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Specify the amount of DRAM reserved for gathering the data used to
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generate the ACPI table.
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 150
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config DISABLE_SPI_FLASH_ROM_SHARING
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def_bool n
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help
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Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
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which indicates a board level ROM transaction request. This
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removes arbitration with board and assumes the chipset controls
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the SPI flash bus entirely.
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config DISABLE_KEYBOARD_RESET_PIN
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bool
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help
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Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L.
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config FEATURE_DYNAMIC_DPTC
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bool
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depends on SOC_AMD_COMMON_BLOCK_ACPI_DPTC
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help
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Selected by mainboards that implement support for ALIB
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to enable dynamic DPTC.
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config FEATURE_TABLET_MODE_DPTC
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bool
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depends on SOC_AMD_COMMON_BLOCK_ACPI_DPTC
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help
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Selected by mainboards that implement support for ALIB to
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switch default and tablet mode.
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menu "PSP Configuration Options"
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config AMDFW_CONFIG_FILE
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string "AMD PSP Firmware config file"
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default "src/soc/amd/mendocino/fw.cfg"
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help
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Specify the path/location of AMD PSP Firmware config file.
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config PSP_DISABLE_POSTCODES
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bool "Disable PSP post codes"
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help
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Disables the output of port80 post codes from PSP.
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config PSP_POSTCODES_ON_ESPI
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bool "Use eSPI bus for PSP post codes"
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default y
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depends on !PSP_DISABLE_POSTCODES
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help
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Select to send PSP port80 post codes on eSPI bus.
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If not selected, PSP port80 codes will be sent on LPC bus.
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config PSP_LOAD_MP2_FW
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bool
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default n
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help
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Include the MP2 firmwares and configuration into the PSP build.
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If unsure, answer 'n'
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config PSP_UNLOCK_SECURE_DEBUG
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bool "Unlock secure debug"
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default y
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help
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Select this item to enable secure debug options in PSP.
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config HAVE_PSP_WHITELIST_FILE
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bool "Include a debug whitelist file in PSP build"
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default n
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help
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Support secured unlock prior to reset using a whitelisted
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serial number. This feature requires a signed whitelist image
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and bootloader from AMD.
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If unsure, answer 'n'
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config PSP_WHITELIST_FILE
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string "Debug whitelist file path"
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depends on HAVE_PSP_WHITELIST_FILE
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default "site-local/3rdparty/amd_blobs/mendocino/PSP/wtl-mdn.sbin"
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config HAVE_SPL_FILE
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bool "Have a mainboard specific SPL table file"
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default n
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help
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Have a mainboard specific Security Patch Level (SPL) table file. SPL file
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is required to support PSP FW anti-rollback and needs to be created by AMD.
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The default SPL file applies to all boards that use the concerned SoC and
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is dropped under 3rdparty/blobs. The mainboard specific SPL file override
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can be applied through SPL_TABLE_FILE config.
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If unsure, answer 'n'
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config SPL_TABLE_FILE
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string "SPL table file"
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depends on HAVE_SPL_FILE
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin"
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config HAVE_SPL_RW_AB_FILE
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bool "Have a separate mainboard-specific SPL file in RW A/B partitions"
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default n
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depends on HAVE_SPL_FILE
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depends on VBOOT_SLOTS_RW_AB
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help
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Have separate mainboard-specific Security Patch Level (SPL) table
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file for the RW A/B FMAP partitions. See the help text of
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HAVE_SPL_FILE for a more detailed description.
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config SPL_RW_AB_TABLE_FILE
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string "Separate SPL table file for RW A/B partitions"
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depends on HAVE_SPL_RW_AB_FILE
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin"
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config PSP_SOFTFUSE_BITS
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string "PSP Soft Fuse bits to enable"
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default "34 28 6"
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help
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Space separated list of Soft Fuse bits to enable.
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Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
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Bit 7: Disable PSP postcodes on Renoir and newer chips only
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(Set by PSP_DISABLE_PORT80)
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Bit 15: PSP debug output destination:
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0=SoC MMIO UART, 1=IO port 0x3F8
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Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
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See #55758 (NDA) for additional bit definitions.
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config PSP_VERSTAGE_FILE
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string "Specify the PSP_verstage file path"
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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default "\$(obj)/psp_verstage.bin"
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help
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Add psp_verstage file to the build & PSP Directory Table
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config PSP_VERSTAGE_SIGNING_TOKEN
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string "Specify the PSP_verstage Signature Token file path"
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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default ""
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help
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Add psp_verstage signature token to the build & PSP Directory Table
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endmenu
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config VBOOT
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config VBOOT_STARTS_BEFORE_BOOTBLOCK
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def_bool n
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depends on VBOOT
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select ARCH_VERSTAGE_ARMV7
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help
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Runs verstage on the PSP. Only available on
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certain ChromeOS branded parts from AMD.
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config VBOOT_HASH_BLOCK_SIZE
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hex
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default 0x9000
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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help
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|
Because the bulk of the time in psp_verstage to hash the RO cbfs is
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spent in the overhead of doing svc calls, increasing the hash block
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|
size significantly cuts the verstage hashing time as seen below.
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4k takes 180ms
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|
16k takes 44ms
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|
32k takes 33.7ms
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36k takes 32.5ms
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|
There's actually still room for an even bigger stack, but we've
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reached a point of diminishing returns.
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|
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config CMOS_RECOVERY_BYTE
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|
hex
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|
default 0x51
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|
depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
|
|
help
|
|
If the workbuf is not passed from the PSP to coreboot, set the
|
|
recovery flag and reboot. The PSP will read this byte, mark the
|
|
recovery request in VBNV, and reset the system into recovery mode.
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|
|
|
This is the byte before the default first byte used by VBNV
|
|
(0x26 + 0x0E - 1)
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|
|
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if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK
|
|
|
|
config RWA_REGION_ONLY
|
|
string
|
|
default "apu/amdfw_a apu/amdfw_a_body"
|
|
help
|
|
Add a space-delimited list of filenames that should only be in the
|
|
RW-A section.
|
|
|
|
endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK
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|
|
|
if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
|
|
|
|
config RWB_REGION_ONLY
|
|
string
|
|
default "apu/amdfw_b apu/amdfw_b_body"
|
|
help
|
|
Add a space-delimited list of filenames that should only be in the
|
|
RW-B section.
|
|
|
|
endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
|
|
|
|
endif # SOC_AMD_REMBRANDT_BASE
|