debb11fc1f
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
36 lines
925 B
Plaintext
36 lines
925 B
Plaintext
Non-automatic IO-Addresses
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The following dynamic IO BARs are used on the ICH7 for the Kontron Default BIOS:
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GPIOBASE 0x480 (64 bytes)
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PMBASE 0x800 (128 bytes)
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SMBASE 0x400 (32 bytes)
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HWMON 0xa00 (??)
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The following dynamic IO BARs are used on the ICH7 for the Getac Default BIOS:
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GPIOBASE 0x1180 (64 bytes)
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PMBASE 0x1000 (128 bytes)
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SMBASE 0x18e0 (32 bytes)
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The Getac also needs an IO Trapped area of 0x0C bytes (defaults to 0x800)
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coreboot:
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GPIOBASE 0x480 (64 bytes)
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PMBASE 0x500 (128 bytes)
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SMBASE 0x400 (32 bytes)
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HWMON 0xa00 (??)
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NOTE: Coreboot sets the SMBASE to 0xf00 in auto.c. But it gets relocated
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in stage2 because its a "normal BAR" (to 0x2080 in one case here).
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This is not unhealthy but at least confusing. We should provide a method to
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nail down certain resources for stage2.
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For a list of static I/O space allocation look at 6.3.1 of the ICH7 Family
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Datasheet.
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