Huayang Duan 6ee5559d6a soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell ...

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2019-12-20 17:57:03 +00:00

..

common

src: Replace min/max() with MIN/MAX()

2019-12-20 17:49:29 +00:00

mt8173

src: Replace min/max() with MIN/MAX()

2019-12-20 17:49:29 +00:00

mt8183

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

2019-12-20 17:57:03 +00:00

Kconfig

soc: Add Kconfig for each soc vendor

2017-10-23 17:18:32 +00:00