6f66f414a0
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
28 lines
979 B
C
28 lines
979 B
C
#include <arch/io.h>
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/* Just re-define these instead of including gm45.h. It blows up romcc. */
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#define D0F0_PCIEXBAR_LO 0x60
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#define D0F0_PCIEXBAR_HI 0x64
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static void bootblock_northbridge_init(void)
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{
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uint32_t reg;
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/*
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
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* to true. That way all subsequent non-explicit config accesses use
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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*/
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reg = 0;
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pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg);
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reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
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}
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