7011fa1135
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
36 lines
1.0 KiB
C
36 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include "gpio.h"
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/* GPIO pins used by coreboot should be initialized in bootblock */
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static const struct soc_amd_gpio gpio_set_stage_reset[] = {
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/* assert PCIe reset */
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PAD_GPO(GPIO_6, HIGH),
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/* not LLB */
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PAD_GPI(GPIO_12, PULL_UP),
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/* not USB_OC1_L */
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PAD_GPI(GPIO_17, PULL_UP),
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/* not USB_OC2_L */
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PAD_GPI(GPIO_18, PULL_UP),
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/* SDIO eMMC power control */
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PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE),
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/* PCIe Reset to DP0, DP1, J2105, TP, FP */
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PAD_GPO(GPIO_27, HIGH),
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/* eSPI CS# */
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PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
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/* GPP_10G_SELECT => High=10G, Low=x2 NVME (work with AGPIO89) */
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PAD_GPO(GPIO_42, LOW),
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/* FANOUT0 */
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PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
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/* APU_COMBO_GPP_SW => High=SATA, Low=x2 NVME (work with EGPIO42) */
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PAD_GPO(GPIO_89, LOW),
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/* PC beep to codec */
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PAD_NF(GPIO_91, SPKR, PULL_NONE),
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};
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void mainboard_program_early_gpios(void)
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{
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gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
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}
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