7039edd2da
For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.
Some exceptions allowed are described below and in code comments.
SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.
google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.
TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.
Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
137 lines
4.1 KiB
C
137 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/hpet.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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#include <bootmode.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8772f/it8772f.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <superio/smsc/lpc47n207/lpc47n207.h>
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#define SUPERIO_DEV PNP_DEV(0x2e, 0)
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#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
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void mainboard_late_rcba_config(void)
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{
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P1IP WLAN INTA -> PIRQB
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* D28IP_P4IP ETH0 INTB -> PIRQC
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* D29IP_E1P EHCI1 INTA -> PIRQD
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* D26IP_E2P EHCI2 INTA -> PIRQE
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQG
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* D31IP_TTIP THRT INTC -> PIRQH
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* D27IP_ZIP HDA INTA -> PIRQG (MSI)
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*/
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/* Device interrupt pin register (board specific) */
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RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
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RCBA32(D30IP) = (NOINT << D30IP_PIP);
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RCBA32(D29IP) = (INTA << D29IP_E1P);
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RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
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(INTB << D28IP_P4IP);
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RCBA32(D27IP) = (INTA << D27IP_ZIP);
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RCBA32(D26IP) = (INTA << D26IP_E2P);
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RCBA32(D25IP) = (NOINT << D25IP_LIP);
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RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
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/* Device interrupt route registers */
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DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
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DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
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DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
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DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
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DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
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DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
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}
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static void setup_sio_gpios(void)
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{
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/*
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* GPIO10 as USBPWRON12#
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* GPIO12 as USBPWRON13#
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*/
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it8772f_gpio_setup(SUPERIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05);
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/*
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* GPIO22 as wake SCI#
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*/
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it8772f_gpio_setup(SUPERIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04);
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/*
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* GPIO32 as EXTSMI#
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*/
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it8772f_gpio_setup(SUPERIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04);
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/*
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* GPIO45 as LED_POWER#
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*/
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it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */,
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(0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */,
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(0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */,
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SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
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/*
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* GPIO51 as USBPWRON8#
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* GPIO52 as USBPWRON1#
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*/
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it8772f_gpio_setup(SUPERIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06);
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it8772f_gpio_setup(SUPERIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);
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}
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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const uint8_t spdaddr[] = {0xa0, 0x00, 0xa4, 0x00};
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memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
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/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[2], 0x52, id_only);
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* enabled power USB oc pin */
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{ 1, 1, 0 }, /* P0: Front port (OC0) */
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{ 1, 0, 1 }, /* P1: Back port (OC1) */
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{ 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
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{ 1, 0, -1 }, /* P3: MMC (no OC) */
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{ 1, 1, 2 }, /* P4: Front port (OC2) */
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{ 0, 0, -1 }, /* P5: Empty */
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{ 0, 0, -1 }, /* P6: Empty */
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{ 0, 0, -1 }, /* P7: Empty */
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{ 1, 0, 4 }, /* P8: Back port (OC4) */
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{ 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
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{ 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
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{ 0, 0, -1 }, /* P11: Empty */
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{ 1, 0, 6 }, /* P12: Back port (OC6) */
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{ 1, 0, 5 }, /* P13: Back port (OC5) */
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};
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void bootblock_mainboard_early_init(void)
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{
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if (CONFIG(DRIVERS_UART_8250IO))
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try_enabling_LPC47N207_uart();
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setup_sio_gpios();
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/* Early SuperIO setup */
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it8772f_ac_resume_southbridge(SUPERIO_DEV);
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ite_kill_watchdog(GPIO_DEV);
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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