70a815a1e0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I80f11b8f0c2a1fdccbc322c3c4783c61684ff37a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55634 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
374 lines
11 KiB
Plaintext
374 lines
11 KiB
Plaintext
fw_config
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field AUDIO 8 10
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option NONE 0
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option ADL_MAX98373_ALC5682I_I2S 1
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end
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end
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chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# FSP configuration
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register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0
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register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A port 1
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Type-A port 2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
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# Sagv Configuration
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register "SaGv" = "SaGv_Enabled"
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# Enable CNVi Bluetooth
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register "CnviBtCore" = "true"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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#Enable PCH PCIE RP 4 using CLK 5
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register "pch_pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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# Enable PCH PCIE RP 5 using CLK 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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# Enable PCH PCIE RP 9 using CLK 3
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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#Enable PCH PCIE RP 10 using CLK 1
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register "pch_pcie_rp[PCH_RP(10)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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# Hybrid storage mode
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register "HybridStorageMode" = "1"
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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}"
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# Enable EDP in PortA
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register "DdiPortAConfig" = "1"
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# Enable HDMI in Port B
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register "ddi_ports_config" = "{
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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register "s0ix_enable" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
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register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
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register "PchHdaIDispCodecEnable" = "1"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref pcie5 on end
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device ref igpu on end
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device ref dtt on end
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device ref ipu on
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chip drivers/intel/mipi_camera
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register "acpi_uid" = "0x50000"
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register "acpi_name" = ""IPU0""
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register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
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register "cio2_num_ports" = "2"
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register "cio2_lanes_used" = "{2,2}"
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register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
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register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
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register "cio2_prt[0]" = "2"
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register "cio2_prt[1]" = "1"
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device generic 0 on end
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end
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end
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device ref pcie4_0 on end
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device ref pcie4_1 on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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register "type" = "UPC_TYPE_HUB"
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""TypeC Port 1""
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""TypeC Port 2""
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref tcss_dma0 on end
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device ref xhci on
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chip drivers/usb/acpi
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register "desc" = ""Root Hub""
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register "type" = "UPC_TYPE_HUB"
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port10 on end
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end
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end
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end
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_H3_IRQ)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on
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probe AUDIO ADL_MAX98373_ALC5682I_I2S
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end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "0"
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register "imon_slot_no" = "1"
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register "uid" = "0"
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register "desc" = ""Right Speaker Amp""
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register "name" = ""MAXR""
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device i2c 31 on
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probe AUDIO ADL_MAX98373_ALC5682I_I2S
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end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "2"
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register "imon_slot_no" = "3"
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register "uid" = "1"
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register "desc" = ""Left Speaker Amp""
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register "name" = ""MAXL""
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device i2c 32 on
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probe AUDIO ADL_MAX98373_ALC5682I_I2S
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end
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end
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end
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device ref i2c1 on
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chip drivers/intel/mipi_camera
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register "acpi_hid" = ""OVTI5675""
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register "acpi_uid" = "0"
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register "acpi_name" = ""CAM0""
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register "chip_name" = ""Ov 5675 Camera""
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register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
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register "ssdb.lanes_used" = "2"
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register "ssdb.vcm_type" = "0x0C"
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register "vcm_name" = ""VCM0""
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register "num_freq_entries" = "1"
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register "link_freq[0]" = "450000000"
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register "remote_name" = ""IPU0""
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register "has_power_resource" = "1"
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#Controls
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register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
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register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
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register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
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register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
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#_ON
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register "on_seq.ops_cnt" = "4"
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register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
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register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
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register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
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register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
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#_OFF
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register "off_seq.ops_cnt" = "3"
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register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
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register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
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register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
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device i2c 36 on end
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end
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chip drivers/intel/mipi_camera
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register "acpi_uid" = "3"
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register "acpi_name" = ""VCM0""
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register "chip_name" = ""DW AF VCM""
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register "device_type" = "INTEL_ACPI_CAMERA_VCM"
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register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
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register "vcm_compat" = ""dongwoon,dw9714""
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device i2c 0C on end
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end
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end
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device ref i2c2 on end
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device ref i2c3 on end
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device ref heci1 on end
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device ref sata on end
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device ref i2c5 on
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chip drivers/intel/mipi_camera
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register "acpi_hid" = ""OVTI5675""
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register "acpi_uid" = "0"
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register "acpi_name" = ""CAM1""
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register "chip_name" = ""Ov 5675 Camera""
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register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
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register "ssdb.lanes_used" = "2"
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register "num_freq_entries" = "1"
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register "link_freq[0]" = "450000000"
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register "remote_name" = ""IPU0""
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register "has_power_resource" = "1"
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#Controls
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register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
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register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
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register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
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register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
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#_ON
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register "on_seq.ops_cnt" = "4"
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register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
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register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
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register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
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register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
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#_OFF
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register "off_seq.ops_cnt" = "3"
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register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
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register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
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register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
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device i2c 36 on end
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end
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end
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device ref pcie_rp1 on end
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device ref pcie_rp3 on end # W/A to FSP issue
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device ref pcie_rp4 on end # W/A to FSP issue
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device ref pcie_rp5 on end
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device ref pcie_rp6 on end
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device ref pcie_rp8 on end
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device ref pcie_rp9 on end
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device ref pcie_rp10 on end
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device ref uart0 on end
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device ref gspi0 on end
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device ref p2sb on end
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device ref hda on
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chip drivers/intel/soundwire
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device generic 0 on
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chip drivers/soundwire/alc711
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# SoundWire Link 0 ID 1
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register "desc" = ""Headset Codec""
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device generic 0.1 on end
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end
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end
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end
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end
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device ref smbus on end
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end
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end
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