In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
79 lines
2.3 KiB
C
79 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "cs5530.h"
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/**
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* Initialize the IDE controller.
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*
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* Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
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* enable or disable the primary and secondary IDE interface, respectively.
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*
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* @param dev The device to use.
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*/
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static void ide_init(struct device *dev)
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{
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uint8_t reg8;
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struct southbridge_amd_cs5530_config *conf = dev->chip_info;
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reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
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/* Enable/disable the primary IDE interface. */
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if (conf->ide0_enable) {
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reg8 |= PRIMARY_IDE_ENABLE;
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} else {
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reg8 &= ~(PRIMARY_IDE_ENABLE);
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}
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/* Enable/disable the secondary IDE interface. */
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if (conf->ide1_enable) {
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reg8 |= SECONDARY_IDE_ENABLE;
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} else {
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reg8 &= ~(SECONDARY_IDE_ENABLE);
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}
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pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
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printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
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conf->ide0_enable ? "enabled" : "disabled");
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printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
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conf->ide1_enable ? "enabled" : "disabled");
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.enable = 0,
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.scan_bus = scan_static_bus,
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.ops_pci = 0,
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};
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static const struct pci_driver ide_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_CYRIX,
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.device = PCI_DEVICE_ID_CYRIX_5530_IDE,
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};
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