11e743ce26
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24 Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0 Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8798 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
96 lines
2.6 KiB
C
96 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* tlb.c: System intructions for TLB maintenance.
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* Reference: ARM Architecture Reference Manual, ARMv8-A edition
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*/
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#include <stdint.h>
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#include <arch/lib_helpers.h>
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/* TLBIALL */
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void tlbiall_el1(void)
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{
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__asm__ __volatile__("tlbi alle1\n\t" : : : "memory");
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}
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void tlbiall_el2(void)
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{
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__asm__ __volatile__("tlbi alle2\n\t" : : : "memory");
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}
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void tlbiall_el3(void)
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{
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__asm__ __volatile__("tlbi alle3\n\t" : : : "memory");
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}
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void tlbiall_current(void)
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{
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uint32_t el = get_current_el();
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tlbiall(el);
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}
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void tlbiall(uint32_t el)
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{
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SWITCH_CASE_TLBI(tlbiall, el);
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}
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/* TLBIALLIS */
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void tlbiallis_el1(void)
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{
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__asm__ __volatile__("tlbi alle1is\n\t" : : : "memory");
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}
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void tlbiallis_el2(void)
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{
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__asm__ __volatile__("tlbi alle2is\n\t" : : : "memory");
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}
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void tlbiallis_el3(void)
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{
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__asm__ __volatile__("tlbi alle3is\n\t" : : : "memory");
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}
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void tlbiallis_current(void)
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{
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uint32_t el = get_current_el();
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tlbiallis(el);
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}
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void tlbiallis(uint32_t el)
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{
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SWITCH_CASE_TLBI(tlbiallis, el);
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}
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/* TLBIVAA */
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void tlbivaa_el1(uint64_t va)
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{
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__asm__ __volatile__("tlbi vaae1, %0\n\t" : : "r" (va) : "memory");
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}
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