system76-coreboot

Files

Furquan Shaikh 7340efcf19 mb/google/zork: Configure GPIO_40 as drive low in sleep path

This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in
sleep path so that the PERST# to NVMe device keeps asserted until
coreboot reconfigures it as high on S3 resume path. This is similar to
the earlier change for PCIE_RST1_L but helps platforms that use
NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain,
hence it retains state across S3 entry/exit.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie79e946eee8f393863630226ae2183e653030415
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2020-07-01 17:54:43 +00:00

acpi

acpi: Avoid freeing a device twice

2020-07-01 04:52:47 +00:00

arch

src/arch/x86: Ensure $(objgenerated) exists before it's used

2020-06-30 22:27:21 +00:00

commonlib

cbmem: Remove IDs for TSEG and BERT

2020-06-22 22:57:13 +00:00

console

console: Update for vboot before bootblock