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Since commit3bfd7cc(drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since24391321(mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
coreboot is changing all the time and the patches are reabsed when pushed to community, so it is a little difficult to provide stable Bettong code. From now on, AMD provides source code which is validated by QA team. The code is pushed to github https://github.com/BTDC/coreboot The version is identified by a tag. All the changes will be pushed to coreboot community. ===== Version: TCMEF1F0 Release Date: 09/29/2015 Changes from last version: 1. Fix external graphics issue. 2. Add board ID support. 3. Support DDR4. 4. Support SD 2.0. 5. Fix Windows 7 S4 issue. 6. Add GPIO, I2C and UART support. 7. Fix the interrupt routine. 8. Restruct PCI interrupt table (C00/C01). 9. Fix DSDT issue. 10. Fix the PCIe lane map. 11. Lower the TOM to give more MMIO space. 12. Add USB device. 13. Set the USB3 port as unremoveable. 14. Update AGESA to CarrizoPI 1.1.0.1.