73a52d212b
All AGESA headers should be included only through agesawrapper.h I missed this file in the Kahlee cleanup. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <agesawrapper.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
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2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x04, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
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2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x2, 0)
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},
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/* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
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2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x3, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
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2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
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2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0, 0)
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},
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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/* DDI0 - eDP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
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},
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/* DDI1 - DP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
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},
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/* DDI2 - DP */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
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},
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = (void *)PortList,
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.DdiLinkList = (void *)DdiList
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};
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/*---------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This is the stub function will call the host environment through the
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* binary block interface (call-out port) to provide a user hook opportunity.
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*
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* Parameters:
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* @param[in] **PeiServices
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------*/
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VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
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InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
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InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
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}
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