740eee5eec
This field was never meant to be filled out by coreboot, because it can't know what the right value for this will be by the time the OS is running, so anything coreboot could fill in here is premature. This field is only read by the chromeos-specific `crossystem` utility, not by kernel code, so if one does not run through depthcharge there'll be many more broken assumptions in CNVS anyway. Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "onboard.h"
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#define FLAG_SPI_WP 0
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#define FLAG_REC_MODE 1
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#include "ec.h"
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#include <ec/smsc/mec1308/ec.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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/* Recovery: GPIO42 = CHP3_REC_MODE# */
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{GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(),
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"presence"},
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{100, ACTIVE_HIGH, get_lid_switch(), "lid"},
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/* Power Button */
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{101, ACTIVE_LOW, get_power_switch(), "power"},
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/* Did we load the VGA Option ROM? */
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/* -1 indicates that this is a pseudo GPIO */
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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static bool raw_write_protect_state(void)
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{
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return get_gpio(GPIO_SPI_WP);
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}
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static bool raw_recovery_mode_switch(void)
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{
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return !get_gpio(GPIO_REC_MODE);
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}
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int get_lid_switch(void)
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{
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return ec_read(0x83) & 1;
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}
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int get_power_switch(void)
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{
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const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
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u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
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return (gen_pmcon_1 >> 9) & 1;
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}
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int get_write_protect_state(void)
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{
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const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
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return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
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}
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int get_recovery_mode_switch(void)
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{
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const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
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return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
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}
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void init_bootmode_straps(void)
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{
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u32 flags = 0;
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const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
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/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
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if (raw_write_protect_state())
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flags |= (1 << FLAG_SPI_WP);
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/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
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if (raw_recovery_mode_switch())
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flags |= (1 << FLAG_REC_MODE);
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pci_s_write_config32(dev, SATA_SP, flags);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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