Greg Watson 746376d641 cache.c ...

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2004-01-22 01:00:22 +00:00

..

arch

updated for other boards

2004-01-22 01:00:07 +00:00

boot

- O2, enums, and switch statements work in romcc

2003-10-11 06:20:25 +00:00

config

allow TTYS0_DIV to be set explicitly

2004-01-14 17:08:14 +00:00

console

allow TTYS0_DIV to be set explicitly

2004-01-14 17:08:14 +00:00

cpu

cache.c

2004-01-22 01:00:22 +00:00

devices

Change PCI_BRIDGE_CONTROL to PCI_BRIDGE_CTL_VGA

2004-01-08 21:15:49 +00:00

include

- O2, enums, and switch statements work in romcc

2003-10-11 06:20:25 +00:00

lib

used pre-hardwaremain()

2003-11-15 15:31:12 +00:00

mainboard

try to get memory mapped i/o to work

2004-01-22 00:45:13 +00:00

northbridge

small fixes

2004-01-14 15:46:30 +00:00

pc80

trying to get it right...

2004-01-21 23:50:56 +00:00

pmc/altimus/mpc7410

moved cpu code to cpu/ppc/mpc74xx

2003-07-24 21:05:02 +00:00

ram

- Add missing carriage return in ramtest.c

2003-07-12 01:46:05 +00:00

sdram

remove SMBUS_MEM_DEVICE_[START|END] traces from code.

2003-10-07 14:56:48 +00:00

southbridge

default values seem to work fine

2004-01-21 23:56:37 +00:00

stream

changed routine name

2004-01-21 23:52:49 +00:00

superio/NSC

- O2, enums, and switch statements work in romcc

2003-10-11 06:20:25 +00:00