7e516fbb47
This replaces magic values with defines without changing any value. Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/16339 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
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* Copyright (C) 2016 Sebastian Grzywna <swiftgeek@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2, or (at your option)
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* any later verion of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include "i915_reg.h"
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#include "edid.h"
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#define GMBUS0_ADDR (mmio + 4 * 0)
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#define GMBUS1_ADDR (mmio + 4 * 1)
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#define GMBUS2_ADDR (mmio + 4 * 2)
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#define GMBUS3_ADDR (mmio + 4 * 3)
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#define GMBUS5_ADDR (mmio + 4 * 8)
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#define AT24_ADDR 0x50 /* EDID EEPROM */
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static void wait_rdy(u8 *mmio)
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{
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unsigned try = 100;
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while (try--) {
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if (read32(GMBUS2_ADDR) & GMBUS_HW_RDY)
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return;
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udelay(10);
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}
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}
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static void intel_gmbus_stop_bus(u8 * mmio, u8 bus)
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{
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wait_rdy(mmio);
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write32(GMBUS0_ADDR, bus);
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wait_rdy(mmio);
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write32(GMBUS5_ADDR, 0);
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write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
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| GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT )
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| GMBUS_SLAVE_READ | (AT24_ADDR << 1) );
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wait_rdy(mmio);
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write32(GMBUS5_ADDR, 0);
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write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT);
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write32(GMBUS1_ADDR, 0);
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wait_rdy(mmio);
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write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE
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| (AT24_ADDR << 1) );
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wait_rdy(mmio);
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write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
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write32(GMBUS2_ADDR, GMBUS_INUSE);
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}
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void intel_gmbus_stop(u8 *mmio)
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{
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intel_gmbus_stop_bus(mmio, 6);
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intel_gmbus_stop_bus(mmio, 2);
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}
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void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
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{
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int i;
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slave &= 0x7f;
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edid_size &= 0x1fc;
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wait_rdy(mmio);
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/* 100 KHz, hold 0ns, */
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write32(GMBUS0_ADDR, bus);
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wait_rdy(mmio);
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/* Ensure index bits are disabled. */
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write32(GMBUS5_ADDR, 0);
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write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
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| (slave << 1) );
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wait_rdy(mmio);
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/* Ensure index bits are disabled. */
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write32(GMBUS5_ADDR, 0);
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write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT
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| GMBUS_CYCLE_STOP
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| (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
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for (i = 0; i < edid_size / 4; i++) {
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u32 reg32;
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wait_rdy(mmio);
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reg32 = read32(GMBUS3_ADDR);
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edid[4 * i] = reg32 & 0xff;
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edid[4 * i + 1] = (reg32 >> 8) & 0xff;
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edid[4 * i + 2] = (reg32 >> 16) & 0xff;
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edid[4 * i + 3] = (reg32 >> 24) & 0xff;
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}
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wait_rdy(mmio);
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write32(GMBUS1_ADDR, GMBUS_SW_RDY
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| GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP
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| (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
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wait_rdy(mmio);
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write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );
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write32(GMBUS2_ADDR, GMBUS_INUSE);
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printk (BIOS_SPEW, "EDID:\n");
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for (i = 0; i < 128; i++) {
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printk (BIOS_SPEW, "%02x ", edid[i]);
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if ((i & 0xf) == 0xf)
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printk (BIOS_SPEW, "\n");
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}
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}
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