74b13a5616
The existing KFSN4-DRE support hung during ramstage while initializing AP #3 if a second CPU package was installed. After analyzing the Sun Ultra 40 M2 support code it became apparent that the K8 code cannot function correctly if sequential RAM training is disabled, and that there were a few other missing calls. This patch adds the missing calls, adjust the CAR space to an appropriate level, and explicitly defines the link numbers and connections in devicetree.cb TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12285 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
198 lines
9.7 KiB
Plaintext
198 lines
9.7 KiB
Plaintext
chip northbridge/amd/amdk8/root_complex # Root complex
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device cpu_cluster 0 on # (L)APIC cluster
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chip cpu/amd/socket_F # CPU socket
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device lapic 0 on end # Local APIC of the CPU
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end
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end
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device domain 0 on # PCI domain
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subsystemid 0x1043 0x8162 inherit
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chip northbridge/amd/amdk8 # Northbridge / RAM controller
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register "maximum_memory_capacity" = "0x1000000000" # 64GB
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device pci 18.0 on end # Link 0 == LDT 0
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device pci 18.0 on # Link 1 == LDT 1 [SB on link 1]
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chip southbridge/nvidia/ck804 # Southbridge
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/winbond/w83627thg # Super I/O
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device pnp 2e.0 on # Floppy
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# Set up interface resources
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off end # Parallel port
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device pnp 2e.2 on # Com1
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# Set up interface resources
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Com2
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# Set up interface resources
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io 0x60 = 0x2f8
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irq 0x70 = 3
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# Select correct package I/O pins
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io 0xf1 = 0x04
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end
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device pnp 2e.5 on # PS/2 keyboard & mouse
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# Set up interface resources
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5
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device pnp 2e.8 off end # GPIO 2
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device pnp 2e.9 on end # GPIO 3, GPIO 4
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # Hardware monitor
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# Set up interface resources
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic # DIMM n-0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM n-0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM n-0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM n-0-1-1
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device i2c 53 on end
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end
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chip drivers/generic/generic # DIMM n-1-0-0
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device i2c 54 on end
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end
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chip drivers/generic/generic # DIMM n-1-0-1
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device i2c 55 on end
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end
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chip drivers/generic/generic # DIMM n-1-1-0
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device i2c 56 on end
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end
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chip drivers/generic/generic # DIMM n-1-1-1
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device i2c 57 on end
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end
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chip drivers/i2c/w83793
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register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs
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register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12
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register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40
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register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation)
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register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
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register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
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register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
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register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
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register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2
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register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4
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register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C
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register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C
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register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C
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register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C
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register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C
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register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C
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register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C
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register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C
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register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C
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register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C
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register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C
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register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C
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register "critical_temperature" = "80" # Set critical temperature to 80°C
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register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain
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register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode
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register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything
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register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1)
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register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2)
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register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3)
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register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4)
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register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1)
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register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2)
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register "fan1_nonstop" = "7" # Set Fan 1 minimum speed
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register "fan2_nonstop" = "7" # Set Fan 2 minimum speed
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register "fan3_nonstop" = "7" # Set Fan 3 minimum speed
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register "fan4_nonstop" = "7" # Set Fan 4 minimum speed
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register "fan5_nonstop" = "7" # Set Fan 5 minimum speed
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register "fan6_nonstop" = "7" # Set Fan 6 minimum speed
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register "fan7_nonstop" = "7" # Set Fan 7 minimum speed
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register "fan8_nonstop" = "7" # Set Fan 8 minimum speed
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register "default_speed" = "100" # All fans to full speed on power up
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register "fan1_duty" = "100" # Fan 1 to full speed
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register "fan2_duty" = "100" # Fan 2 to full speed
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register "fan3_duty" = "100" # Fan 3 to full speed
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register "fan4_duty" = "100" # Fan 4 to full speed
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register "fan5_duty" = "100" # Fan 5 to full speed
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register "fan6_duty" = "100" # Fan 6 to full speed
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register "fan7_duty" = "100" # Fan 7 to full speed
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register "fan8_duty" = "100" # Fan 8 to full speed
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register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V
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register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V
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register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V
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register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V
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register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V
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register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V
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register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V
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register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V
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register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V
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register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V
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register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V
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register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V
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register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V
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register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V
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register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V
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register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V
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register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V
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register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V
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register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V
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register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V
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device i2c 0x2f on end
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end
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end
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device pci 1.1 on end # SM 1
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 off end # AC'97 Audio (N/A)
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device pci 4.1 off end # AC'97 Modem (N/A)
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 0
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device pci 8.0 on end # SATA 1
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device pci 9.0 on # Bridge
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device pci 4.0 on end # VGA
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end
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device pci a.0 off end
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device pci b.0 on # Bridge
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device pci 0.0 on end # NIC A
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end
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device pci c.0 on # Bridge
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device pci 0.0 on end # LSI SAS
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end
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device pci d.0 on # Bridge
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device pci 0.0 on end # NIC B
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end
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device pci e.0 on # Bridge
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# Slot # PCI E 0
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end
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device pci f.0 off end
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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end
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end
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device pci 18.0 on end # Link 2 == LDT 2
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 19.0 on end # Link 0 == LDT 0
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device pci 19.0 on end # Link 1 == LDT 1
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device pci 19.0 on end # Link 2 == LDT 2
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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device pci 19.4 on end
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end
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end
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end
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