Eric Lai 74de4b85d1 mb/google/drallion: change servo board debug to UART 0 ...

Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.

BUG=b:139095062
BRANCH=N/A
TEST=Build without error

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>

2019-08-30 10:39:04 +00:00

..

acpi

AUTHORS: Move src/acpi copyrights into AUTHORS file

2019-07-30 11:04:14 +00:00

arch

arm64: Rename arm_tf.c/h to bl31.c/h

2019-08-30 10:37:17 +00:00

commonlib

commonlib/region: Fix up overflow check in region_is_subregion()

2019-08-19 21:12:31 +00:00

console

Add definition for ENV_ROMSTAGE_OR_BEFORE to <rules.h>

2019-08-26 20:59:45 +00:00

cpu

arch/x86: Drop weak attribute on stage_cache

2019-08-28 22:57:17 +00:00

device

Split MAYBE_STATIC to _BSS and _NONZERO variants

2019-08-26 20:56:29 +00:00

drivers

soc/intel: Use common romstage code

2019-08-26 21:08:41 +00:00

ec

Split MAYBE_STATIC to _BSS and _NONZERO variants

2019-08-26 20:56:29 +00:00

include

intel/smm/gen1: Use smm_subregion()

2019-08-28 22:51:27 +00:00

lib

arch/x86: Simplify <arch/early_variables.h>

2019-08-26 22:52:10 +00:00

mainboard

mb/google/drallion: change servo board debug to UART 0

2019-08-30 10:39:04 +00:00

northbridge

intel/haswell: Use smm_subregion()

2019-08-28 22:52:47 +00:00

security

Split MAYBE_STATIC to _BSS and _NONZERO variants

2019-08-26 20:56:29 +00:00

soc

arm64: Rename arm_tf.c/h to bl31.c/h

2019-08-30 10:37:17 +00:00

southbridge

amdfam10: Remove use of __PRE_RAM__

2019-08-26 02:08:42 +00:00

superio

smsc/superio/sio1007: Fix header name

2019-08-27 11:52:13 +00:00

vendorcode

vendorcode/eltan/security/lib: Always include cb_sha.c for bootblock

2019-08-26 13:46:13 +00:00

Kconfig

ACPI S3: Depend on RELOCATABLE_RAMSTAGE

2019-08-22 06:38:13 +00:00