Arthur Heymans 74f9fe6e58 cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE ...

CPU's featuring a non eviction mode cache the whole ROM.
Therefore XIP stages don't need to follow some alignment constraints.

Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

2019-04-25 15:56:28 +00:00

..

acpi.c

cpu/intel/model_206{5,a}x: Rework acpi/cpu.asl

2018-11-30 21:52:10 +00:00

bootblock.c

coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

2019-03-08 08:33:24 +00:00

chip.h

tree: drop last paragraph of GPL copyright header

2015-10-31 21:37:39 +01:00

common.c

src: Move common IA-32 MSRs to <cpu/x86/msr.h>

2018-10-11 21:06:53 +00:00

finalize.c

src: Remove unneeded include "{arch,cpu}/cpu.h"

2018-11-12 09:22:18 +00:00

Kconfig

cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE

2019-04-25 15:56:28 +00:00

Makefile.inc

security/vboot: Add measured boot mode

2019-02-25 22:29:16 +00:00

model_206ax_init.c

src: include <assert.h> when appropriate

2019-04-23 10:01:36 +00:00

model_206ax.h

cpu/intel/model_206ax: Use parallel MP init

2019-01-22 12:16:18 +00:00

stage_cache.c

cpu/intel/sandybridge: Put stage cache into TSEG

2018-04-10 09:30:21 +00:00

tsc_freq.c

cpu/intel/model_206ax: Use tsc monotonic timer

2017-06-09 16:27:19 +02:00