75985f1d0c
OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.
Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR
This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.
Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.
Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.
Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 72
On-line CPU(s) list: 0-71
Thread(s) per core: 2
Core(s) per socket: 18
Socket(s): 2
NUMA node(s): 2
Vendor ID: GenuineIntel
CPU family: 6
Model: 85
Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping: 4
CPU MHz: 140.415
BogoMIPS: 4626.46
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 1024K
L3 cache: 25344K
NUMA node0 CPU(s): 0-17,36-53
NUMA node1 CPU(s): 18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255
inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut
inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20<link>
inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0<global>
ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet)
RX packets 84249 bytes 6371591 (6.0 MiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 8418 bytes 748781 (731.2 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10<host>
loop txqueuelen 1000 (Local Loopback)
RX packets 613 bytes 63906 (62.4 KiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 613 bytes 63906 (62.4 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
[root@localhost ~]# cbmem
36 entries total:
// Lines were cut to avoid checkpatch.pl warnings
Total Time: 96,243,882,140,175,829
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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92 lines
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2019 - 2020 Intel Corporation.
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## Copyright (C) 2019 - 2020 Facebook Inc
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/xeon_sp
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# configure device interrupt routing
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register "ir00_routing" = "0x3210" # IR00, Dev31
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register "ir01_routing" = "0x3210" # IR01, Dev30
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register "ir02_routing" = "0x3210" # IR02, Dev29
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register "ir03_routing" = "0x3210" # IR03, Dev28
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register "ir04_routing" = "0x3210" # IR04, Dev27
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# configure interrupt polarity control
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register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
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register "ipc1" = "0x00000000" # IPC1
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register "ipc2" = "0x00000000" # IPC2
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register "ipc3" = "0x00000000" # IPC3
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# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
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# FB production turbo_ratio_limit is 0x1f1f1f2022222325
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register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
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# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
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register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
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# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
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register "pstate_req_ratio" = "0xa"
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# configure VTD
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register "vtd_support" = "1"
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register "coherency_support" = "1"
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register "ats_support" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host bridge
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device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
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device pci 05.2 on end # Intel Corporation Device 2025
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device pci 05.4 on end # Intel Corporation Device 2026
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device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
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device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
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device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
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device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
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device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
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device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
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device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
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device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
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device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
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device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
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device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
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device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
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device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
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device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
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device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
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device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
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device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
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end
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end
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