7686a56574
Based on damo22's work and my X230 tracing. Works for my X230 in a variety of RAM configs. Also-By: Damien Zammit <damien@zamaudio.com> Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5786 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
319 lines
7.8 KiB
ArmAsm
319 lines
7.8 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/*
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* +--------------------------------+
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* | SMM Handler C Code |
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* +--------------------------------+ 0x14000
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* | SMM Handler Heap |
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* +--------------------------------+ 0x10000
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* | Save State Map Node 0 |
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* | Save State Map Node 1 |
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* | Save State Map Node 2 |
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* | Save State Map Node 3 |
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* | ... |
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* +--------------------------------+ 0xf000
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* | |
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* | |
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* | EARLY DATA (lock, vectors) |
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* +--------------------------------+ 0x8400
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* | SMM Entry Node 0 (+ stack) |
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* +--------------------------------+ 0x8000
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* | SMM Entry Node 1 (+ stack) |
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* | SMM Entry Node 2 (+ stack) |
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* | SMM Entry Node 3 (+ stack) |
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* | ... |
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* +--------------------------------+ 0x7400
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* | |
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* | SMM Handler Assembly Stub |
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* | |
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* +--------------------------------+ TSEG
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*
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*/
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#define LAPIC_ID 0xfee00020
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#define SMM_STACK_SIZE (0x400 - 0x10)
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/* Values for the xchg lock */
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#define SMI_LOCKED 0
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#define SMI_UNLOCKED 1
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#define __PRE_RAM__
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#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
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#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
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#include <northbridge/intel/nehalem/nehalem.h>
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#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
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#elif CONFIG_NORTHBRIDGE_INTEL_HASWELL
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#include <northbridge/intel/haswell/haswell.h>
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#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
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#else
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#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
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#include <northbridge/intel/fsp_sandybridge/northbridge.h>
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#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
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#else
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#error "Northbridge must define TSEG_BAR."
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#endif
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#endif
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/* initially SMM is some sort of real mode. Let gcc know
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* how to treat the SMM handler stub
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*/
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.section ".handler", "a", @progbits
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.code16
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/**
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* SMM code to enable protected mode and jump to the
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* C-written function void smi_handler(u32 smm_revision)
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*
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* All the bad magic is not all that bad after all.
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*/
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smm_handler_start:
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movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */
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addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */
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andl $~1, %edx /* Remove lock bit */
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/* Obtain lock */
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movl %edx, %ebx
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addl $(smm_lock), %ebx
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movw $SMI_LOCKED, %ax
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addr32 xchg %ax, (%ebx)
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cmpw $SMI_UNLOCKED, %ax
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/* Proceed if we got the lock */
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je smm_check_prot_vector
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/* If we did not get the lock, wait for release */
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wait_for_unlock:
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pause
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addr32 movw (%ebx), %ax
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cmpw $SMI_LOCKED, %ax
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je wait_for_unlock
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rsm
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smm_check_prot_vector:
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/* See if we need to adjust protected vector */
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movl %edx, %eax
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addl $(smm_prot_vector), %eax
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addr32 movl (%eax), %ebx
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cmpl $(smm_prot_start), %ebx
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jne smm_check_gdt_vector
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/* Adjust vector with TSEG offset */
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addl %edx, %ebx
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addr32 movl %ebx, (%eax)
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smm_check_gdt_vector:
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/* See if we need to adjust GDT vector */
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movl %edx, %eax
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addl $(smm_gdt_vector + 2), %eax
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addr32 movl (%eax), %ebx
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cmpl $(smm_gdt - smm_handler_start), %ebx
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jne smm_load_gdt
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/* Adjust vector with TSEG offset */
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addl %edx, %ebx
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addr32 movl %ebx, (%eax)
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smm_load_gdt:
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movl $(smm_gdt_vector), %ebx
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addl %edx, %ebx /* TSEG base in %edx */
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data32 lgdt (%ebx)
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movl %cr0, %eax
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andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x1, %eax /* PE = 1 */
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movl %eax, %cr0
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/* Enable protected mode */
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movl $(smm_prot_vector), %eax
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addl %edx, %eax
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data32 ljmp *(%eax)
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.code32
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smm_prot_start:
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/* Use flat data segment */
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movw $0x10, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Get this CPU's LAPIC ID */
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movl $LAPIC_ID, %esi
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movl (%esi), %ecx
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shr $24, %ecx
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/* calculate stack offset by multiplying the APIC ID
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* by 1024 (0x400), and save that offset in ebp.
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*/
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shl $10, %ecx
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movl %ecx, %ebp
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/* We put the stack for each core right above
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* its SMM entry point. Core 0 starts at SMM_BASE + 0x8000,
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* we spare 0x10 bytes for the jump to be sure.
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*/
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movl $0x8010, %eax /* core 0 address */
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addl %edx, %eax /* addjust for TSEG */
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subl %ecx, %eax /* subtract offset, see above */
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movl %eax, %ebx /* Save bottom of stack in ebx */
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/* clear stack */
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cld
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movl %eax, %edi
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movl $(SMM_STACK_SIZE >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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/* set new stack */
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addl $SMM_STACK_SIZE, %ebx
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movl %ebx, %esp
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/* Get SMM revision */
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movl $0xfefc, %ebx /* core 0 address */
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addl %edx, %ebx /* addjust for TSEG */
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subl %ebp, %ebx /* subtract core X offset */
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movl (%ebx), %eax
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pushl %eax
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/* Call 32bit C handler */
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call smi_handler
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/* Release lock */
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movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */
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movl (%eax), %ebx /* Save TSEG_BAR in %ebx */
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andl $~1, %ebx /* Remove lock bit */
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addl $(smm_lock), %ebx
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movw $SMI_UNLOCKED, %ax
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xchg %ax, (%ebx)
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/* To return, just do rsm. It will "clean up" protected mode */
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rsm
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smm_gdt:
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/* The first GDT entry can not be used. Keep it zero */
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.long 0x00000000, 0x00000000
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/* gdt selector 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */
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/* gdt selector 0x10, flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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smm_gdt_end:
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.section ".earlydata", "a", @progbits
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.code16
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.align 4, 0xff
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smm_lock:
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.word SMI_UNLOCKED
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.align 4, 0xff
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smm_prot_vector:
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.long smm_prot_start
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.short 8
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.align 4, 0xff
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smm_gdt_vector:
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.word smm_gdt_end - smm_gdt - 1
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.long smm_gdt - smm_handler_start
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.section ".jumptable", "a", @progbits
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/* This is the SMM jump table. All cores use the same SMM handler
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* for simplicity. But SMM Entry needs to be different due to the
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* save state area. The jump table makes sure all CPUs jump into the
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* real handler on SMM entry.
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*/
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/* This code currently supports up to 16 CPU cores. If more than 16 CPU cores
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* shall be used, below table has to be updated, as well as smm_tseg.ld
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*/
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/* When using TSEG do a relative jump and fix up the CS later since we
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* do not know what our TSEG base is yet.
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*/
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.code16
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jumptable:
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/* core 15 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 14 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 13 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 12 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 11 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 10 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 9 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 8 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 7 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 6 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 5 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 4 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 3 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 2 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 1 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 0 */
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jmp smm_handler_start
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.align 1024, 0x00
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