make their defaults more obvious. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
84 lines
1.3 KiB
Plaintext
84 lines
1.3 KiB
Plaintext
if BOARD_MSI_MS9185
|
|
|
|
config BOARD_SPECIFIC_OPTIONS # dummy
|
|
def_bool y
|
|
select ARCH_X86
|
|
select CPU_AMD_SOCKET_F
|
|
select DIMM_DDR2
|
|
select DIMM_REGISTERED
|
|
select NORTHBRIDGE_AMD_AMDK8
|
|
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
|
|
select SOUTHBRIDGE_BROADCOM_BCM5780
|
|
select SOUTHBRIDGE_BROADCOM_BCM5785
|
|
select SUPERIO_NSC_PC87417
|
|
select HAVE_BUS_CONFIG
|
|
select HAVE_OPTION_TABLE
|
|
select HAVE_PIRQ_TABLE
|
|
select HAVE_MP_TABLE
|
|
select CACHE_AS_RAM
|
|
select HAVE_HARD_RESET
|
|
select LIFT_BSP_APIC_ID
|
|
select BOARD_ROMSIZE_KB_512
|
|
select RAMINIT_SYSINFO
|
|
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
|
select QRANK_DIMM_SUPPORT
|
|
select SET_FIDVID
|
|
|
|
config MAINBOARD_DIR
|
|
string
|
|
default msi/ms9185
|
|
|
|
config DCACHE_RAM_BASE
|
|
hex
|
|
default 0xcc000
|
|
|
|
config DCACHE_RAM_SIZE
|
|
hex
|
|
default 0x04000
|
|
|
|
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
|
hex
|
|
default 0x01000
|
|
|
|
config APIC_ID_OFFSET
|
|
hex
|
|
default 0x8
|
|
|
|
config SB_HT_CHAIN_ON_BUS0
|
|
int
|
|
default 2
|
|
|
|
config MAINBOARD_PART_NUMBER
|
|
string
|
|
default "MS-9185"
|
|
|
|
config MAX_CPUS
|
|
int
|
|
default 4
|
|
|
|
config MAX_PHYSICAL_CPUS
|
|
int
|
|
default 2
|
|
|
|
config HT_CHAIN_END_UNITID_BASE
|
|
hex
|
|
default 0x1
|
|
|
|
config HT_CHAIN_UNITID_BASE
|
|
hex
|
|
default 0x6
|
|
|
|
config IRQ_SLOT_COUNT
|
|
int
|
|
default 11
|
|
|
|
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
|
hex
|
|
default 0x1022
|
|
|
|
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
|
hex
|
|
default 0x2b80
|
|
|
|
endif # BOARD_MSI_MS9185
|