7748ee5ee1
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
59 lines
914 B
Plaintext
59 lines
914 B
Plaintext
if BOARD_BROADCOM_BLAST
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_SOCKET_940
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_BROADCOM_BCM5780
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select SOUTHBRIDGE_BROADCOM_BCM5785
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select SUPERIO_NSC_PC87417
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select BOARD_ROMSIZE_KB_512
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select QRANK_DIMM_SUPPORT
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select DRIVERS_I2C_I2CMUX2
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config MAINBOARD_DIR
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string
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default broadcom/blast
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config DCACHE_RAM_BASE
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hex
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default 0xcf000
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config DCACHE_RAM_SIZE
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hex
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default 0x01000
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "Blast"
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x6
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config IRQ_SLOT_COUNT
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int
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default 11
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endif # BOARD_BROADCOM_BLAST
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