7748ee5ee1
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
75 lines
1.1 KiB
Plaintext
75 lines
1.1 KiB
Plaintext
if BOARD_TYAN_S2912
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_SOCKET_F
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select DIMM_DDR2
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select DIMM_REGISTERED
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_NVIDIA_MCP55
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select HT_CHAIN_DISTRIBUTE
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select MCP55_USE_NIC
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select SUPERIO_WINBOND_W83627HF
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select PARALLEL_CPU_INIT
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select LIFT_BSP_APIC_ID
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select BOARD_ROMSIZE_KB_512
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select QRANK_DIMM_SUPPORT
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select K8_ALLOCATE_IO_RANGE
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config MAINBOARD_DIR
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string
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default tyan/s2912
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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config APIC_ID_OFFSET
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hex
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default 0x10
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config MEM_TRAIN_SEQ
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "S2912"
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config PCI_64BIT_PREF_MEM
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bool
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default n
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config IRQ_SLOT_COUNT
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int
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default 11
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config MCP55_PCI_E_X_0
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int
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default 1
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endif # BOARD_TYAN_S2912
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