Files
system76-coreboot/src/mainboard/asus/dsbf/Kconfig
Kyösti Mälkki c86c6b33e8 intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.

As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.

There are no reasons to have this as board-specific setting.

Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-18 20:52:01 +01:00

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if BOARD_ASUS_DSBF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_LGA771
select SOUTHBRIDGE_INTEL_I3100
select NORTHBRIDGE_INTEL_I5000
select SUPERIO_WINBOND_W83627HF
select BOARD_ROMSIZE_KB_512
select HAVE_PIRQ_TABLE
select DRIVERS_I2C_W83793
select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
default asus/dsbf
config MAINBOARD_PART_NUMBER
string
default "DSBF"
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config IRQ_SLOT_COUNT
int
default 48
config MAX_CPUS
int
default 8
endif