c86c6b33e8
Having same memory region set as both WRPROT and WRBACK using MTRRs is undefined behaviour. This could happen if we allow DCACHE_RAM_BASE to be located within CBFS in SPI flash memory and XIP romstage is at the same location. As SPI master by default decodes all of top 16MiB below 4GiB, initial cache-as-ram line fills may have actually read from SPI flash even in the case DCACHE_RAM_BASE was below the nominal 4GiB - ROM_SIZE. There are no reasons to have this as board-specific setting. Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
35 lines
546 B
Plaintext
35 lines
546 B
Plaintext
if BOARD_ASUS_DSBF
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_LGA771
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select SOUTHBRIDGE_INTEL_I3100
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select NORTHBRIDGE_INTEL_I5000
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select SUPERIO_WINBOND_W83627HF
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select BOARD_ROMSIZE_KB_512
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select HAVE_PIRQ_TABLE
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select DRIVERS_I2C_W83793
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select DRIVERS_GENERIC_IOAPIC
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config MAINBOARD_DIR
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string
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default asus/dsbf
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config MAINBOARD_PART_NUMBER
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string
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default "DSBF"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config IRQ_SLOT_COUNT
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int
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default 48
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config MAX_CPUS
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int
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default 8
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endif
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