1004710579
Replace the use of the old device_t definition inside northbridge/intel/i5000. Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16471 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
332 lines
7.4 KiB
C
332 lines
7.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef NORTHBRIDGE_I5000_RAMINIT_H
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#define NORTHBRIDGE_I5000_RAMINIT_H
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#include <types.h>
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#include <arch/io.h>
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#define I5000_MAX_BRANCH 2
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#define I5000_MAX_CHANNEL 2
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#define I5000_MAX_DIMM_PER_CHANNEL 4
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#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
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#define I5000_FBDRST 0x53
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#define I5000_SPD_BUSY (1 << 12)
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#define I5000_SPD_SBE (1 << 13)
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#define I5000_SPD_WOD (1 << 14)
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#define I5000_SPD_RDO (1 << 15)
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#define I5000_SPD0 0x74
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#define I5000_SPD1 0x76
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#define I5000_SPDCMD0 0x78
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#define I5000_SPDCMD1 0x7c
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#define I5000_FBDHPC 0x4f
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#define I5000_FBDST 0x4b
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#define I5000_FBDHPC_STATE_RESET 0x00
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#define I5000_FBDHPC_STATE_INIT 0x10
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#define I5000_FBDHPC_STATE_READY 0x20
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#define I5000_FBDHPC_STATE_ACTIVE 0x30
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#define I5000_FBDISTS0 0x58
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#define I5000_FBDISTS1 0x5a
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#define I5000_FBDLVL0 0x44
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#define I5000_FBDLVL1 0x45
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#define I5000_FBDICMD0 0x46
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#define I5000_FBDICMD1 0x47
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#define I5000_FBDICMD_IDLE 0x00
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#define I5000_FBDICMD_TS0 0x80
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#define I5000_FBDICMD_TS1 0x90
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#define I5000_FBDICMD_TS2 0xa0
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#define I5000_FBDICMD_TS3 0xb0
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#define I5000_FBDICMD_TS2_MERGE 0xd0
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#define I5000_FBDICMD_TS2_NOMERGE 0xe0
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#define I5000_FBDICMD_ALL_ONES 0xf0
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#define I5000_AMBPRESENT0 0x64
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#define I5000_AMBPRESENT1 0x66
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#define I5000_FBDSBTXCFG0 0xc0
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#define I5000_FBDSBTXCFG1 0xc1
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#define I5000_PROCENABLE 0xf0
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#define I5000_FBD0IBPORTCTL 0x180
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#define I5000_FBD0IBTXPAT2EN 0x1a8
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#define I5000_FBD0IBRXPAT2EN 0x1ac
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#define I5000_FBD0IBTXMSK 0x18c
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#define I5000_FBD0IBRXMSK 0x190
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#define I5000_FBDPLLCTRL 0x1c0
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/* dev 16, function 1 registers */
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#define I5000_MC 0x40
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#define I5000_DRTA 0x48
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#define I5000_DRTB 0x4c
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#define I5000_ERRPERR 0x50
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#define I5000_MCA 0x58
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#define I5000_TOLM 0x6c
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#define I5000_MIR0 0x80
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#define I5000_MIR1 0x84
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#define I5000_MIR2 0x88
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#define I5000_AMIR0 0x8c
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#define I5000_AMIR1 0x90
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#define I5000_AMIR2 0x94
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#define I5000_FERR_FAT_FBD 0x98
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#define I5000_NERR_FAT_FBD 0x9c
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#define I5000_FERR_NF_FBD 0xa0
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#define I5000_NERR_NF_FBD 0xa4
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#define I5000_EMASK_FBD 0xa8
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#define I5000_ERR0_FBD 0xac
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#define I5000_ERR1_FBD 0xb0
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#define I5000_ERR2_FBD 0xb4
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#define I5000_MCERR_FBD 0xb8
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#define I5000_NRECMEMA 0xbe
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#define I5000_NRECMEMB 0xc0
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#define I5000_NRECFGLOG 0xc4
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#define I5000_NRECMEMA 0xbe
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#define I5000_NRECFBDA 0xc8
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#define I5000_NRECFBDB 0xcc
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#define I5000_NRECFBDC 0xd0
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#define I5000_NRECFBDD 0xd4
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#define I5000_NRECFBDE 0xd8
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#define I5000_REDMEMB 0x7c
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#define I5000_RECMEMA 0xe2
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#define I5000_RECMEMB 0xe4
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#define I5000_RECFGLOG 0xe8
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#define I5000_RECFBDA 0xec
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#define I5000_RECFBDB 0xf0
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#define I5000_RECFBDC 0xf4
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#define I5000_RECFBDD 0xf8
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#define I5000_RECFBDE 0xfc
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#define I5000_FBDTOHOSTGRCFG0 0x160
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#define I5000_FBDTOHOSTGRCFG1 0x164
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#define I5000_HOSTTOFBDGRCFG 0x168
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#define I5000_GRFBDLVLDCFG 0x16c
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#define I5000_GRHOSTFULLCFG 0x16d
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#define I5000_GRBUBBLECFG 0x16e
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#define I5000_GRFBDTOHOSTDBLCFG 0x16f
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/* dev 16, function 2 registers */
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#define I5000_FERR_GLOBAL 0x40
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#define I5000_NERR_GLOBAL 0x44
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/* dev 21, function 0 registers */
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#define I5000_MTR0 0x80
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#define I5000_MTR1 0x84
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#define I5000_MTR2 0x88
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#define I5000_MTR3 0x8c
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#define I5000_DMIR0 0x90
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#define I5000_DMIR1 0x94
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#define I5000_DMIR2 0x98
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#define I5000_DMIR3 0x9c
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#define I5000_DMIR4 0xa0
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#define DEFAULT_AMBASE ((u8 *)0xfe000000)
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/* AMB function 1 registers */
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#define AMB_FBDSBCFGNXT 0x54
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#define AMB_FBDLOCKTO 0x68
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#define AMB_EMASK 0x8c
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#define AMB_FERR 0x90
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#define AMB_NERR 0x94
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#define AMB_CMD2DATANXT 0xe8
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/* AMB function 3 registers */
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#define AMB_DAREFTC 0x70
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#define AMB_DSREFTC 0x74
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#define AMB_DRT 0x78
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#define AMB_DRC 0x7c
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#define AMB_MBCSR 0x40
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#define AMB_MBADDR 0x44
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#define AMB_MBLFSRSED 0xa4
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/* AMB function 4 registers */
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#define AMB_DCALCSR 0x40
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#define AMB_DCALADDR 0x44
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#define AMB_DCALCSR_START (1 << 31)
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#define AMB_DCALCSR_OPCODE_NOP 0x00
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#define AMB_DCALCSR_OPCODE_REFRESH 0x01
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#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02
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#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03
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#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05
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#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c
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#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
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#define AMB_DDR2ODTC 0xfc
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#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
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#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
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#define FBDIMM_SPD_FTB 0x08
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#define FBDIMM_SPD_MTB_DIVIDEND 0x09
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#define FBDIMM_SPD_MTB_DIVISOR 0x0a
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#define FBDIMM_SPD_MIN_TCK 0x0b
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#define FBDIMM_SPD_CAS_LATENCIES 0x0d
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#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
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#define FBDIMM_SPD_T_WR 0x10
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#define FBDIMM_SPD_T_RCD 0x13
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#define FBDIMM_SPD_T_RRD 0x14
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#define FBDIMM_SPD_T_RP 0x15
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#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
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#define FBDIMM_SPD_T_RAS 0x17
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#define FBDIMM_SPD_T_RC 0x18
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#define FBDIMM_SPD_T_RFC 0x19
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#define FBDIMM_SPD_T_WTR 0x1b
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#define FBDIMM_SPD_T_RTP 0x1c
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#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
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#define FBDIMM_SPD_ODT 0x4f
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#define FBDIMM_SPD_T_REFI 0x20
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#define FBDIMM_SPD_T_BB 0x83
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#define FBDIMM_SPD_CMD2DATA_800 0x54
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#define FBDIMM_SPD_CMD2DATA_667 0x55
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#define FBDIMM_SPD_CMD2DATA_533 0x56
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void i5000_fbdimm_init(void);
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#define I5000_BURST4 0x01
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#define I5000_BURST8 0x02
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#define I5000_BURST_CHOP 0x80
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#define I5000_ODT_50 4
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#define I5000_ODT_75 2
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#define I5000_ODT_150 1
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enum ddr_speeds {
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DDR_533MHZ,
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DDR_667MHZ,
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DDR_MAX,
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};
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struct i5000_fbdimm {
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struct i5000_fbd_branch *branch;
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struct i5000_fbd_channel *channel;
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struct i5000_fbd_setup *setup;
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enum ddr_speeds speed;
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int num;
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int present:1;
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u32 ambase;
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/* SPD data */
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u8 amb_personality_bytes[14];
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u8 banks;
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u8 rows;
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u8 columns;
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u8 ranks;
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u8 odt;
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u8 sdram_width;
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u8 mtb_divisor;
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u8 mtb_dividend;
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u8 t_ck_min;
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u8 min_cas_latency;
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u8 t_rrd;
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u16 t_rfc;
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u8 t_wtr;
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u8 t_refi;
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u8 cmd2datanxt[DDR_MAX];
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u16 vendor;
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u16 device;
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/* memory rank size in MB */
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int ranksize;
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};
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struct i5000_fbd_channel {
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struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
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struct i5000_fbd_branch *branch;
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struct i5000_fbd_setup *setup;
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int num;
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int used;
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int highest_amb;
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int columns;
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int rows;
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int ranks;
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int banks;
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int width;
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/* memory size in MB on this channel */
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int totalmem;
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};
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struct i5000_fbd_branch {
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struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
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struct i5000_fbd_setup *setup;
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pci_devfn_t branchdev;
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int num;
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int used;
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/* memory size in MB on this branch */
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int totalmem;
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};
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enum odt {
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ODT_150OHM=1,
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ODT_50OHM=4,
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ODT_75OHM=2,
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};
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enum bl {
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BL_BL4=1,
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BL_BL8=2,
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};
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struct i5000_fbd_setup {
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struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
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struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
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enum bl bl;
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enum ddr_speeds ddr_speed;
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int single_channel:1;
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u32 tolm;
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/* global SDRAM timing parameters */
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u8 t_al;
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u8 t_cl;
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u8 t_ras;
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u8 t_wrc;
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u8 t_rc;
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u8 t_rfc;
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u8 t_rrd;
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u8 t_ref;
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u8 t_w2rdr;
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u8 t_r2w;
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u8 t_w2r;
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u8 t_r2r;
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u8 t_w2w;
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u8 t_wtr;
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u8 t_rcd;
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u8 t_rp;
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u8 t_wr;
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u8 t_rtp;
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/* memory size in MB */
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int totalmem;
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};
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int mainboard_set_fbd_clock(int);
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#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff)))
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#endif
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