77d5e7481b
Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
120 lines
3.1 KiB
Plaintext
120 lines
3.1 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_INTEL_HASWELL
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bool
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select CPU_INTEL_HASWELL
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select CACHE_MRC_SETTINGS
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select INTEL_DDI
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select INTEL_GMA_ACPI
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select C_ENVIRONMENT_BOOTBLOCK
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# select BOOTBLOCK_CONSOLE TODO: route LPC
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if NORTHBRIDGE_INTEL_HASWELL
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config HASWELL_VBOOT_IN_BOOTBLOCK
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depends on VBOOT
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bool "Start verstage in bootblock"
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default y
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_SEPARATE_VERSTAGE
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help
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Haswell can either start verstage in a separate stage
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right after the bootblock has run or it can start it
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after romstage for compatibility reasons.
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Haswell however uses a mrc.bin to initialse memory which
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needs to be located at a fixed offset. Therefore even with
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a separate verstage starting after the bootblock that same
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binary is used meaning a jump is made from RW to the RO region
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and back to the RW region after the binary is done.
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config VBOOT
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select VBOOT_OPROM_MATTERS
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select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK
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config VGA_BIOS_ID
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string
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default "8086,0166"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config CACHE_MRC_SIZE_KB
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int
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default 512
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config DCACHE_RAM_BASE
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hex
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default 0xff7c0000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x30000
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help
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The amount of cache-as-ram region required by the reference code.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x2000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config HAVE_MRC
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bool "Add a System Agent binary"
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help
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Select this option to add a System Agent binary to
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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config MRC_FILE
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string "Intel System Agent path and filename"
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depends on HAVE_MRC
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default "mrc.bin"
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help
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The path and filename of the file to use as System Agent
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binary.
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config PRE_GRAPHICS_DELAY
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int "Graphics initialization delay in ms"
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default 0
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help
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On some systems, coreboot boots so fast that connected monitors
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(mostly TVs) won't be able to wake up fast enough to talk to the
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VBIOS. On those systems we need to wait for a bit before executing
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the VBIOS.
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# The UEFI System Agent binary needs to be at a fixed offset in the flash
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# and can therefore only reside in the COREBOOT fmap region
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config RO_REGION_ONLY
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string
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depends on VBOOT
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default "mrc.bin"
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endif
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