7809eb8db6
Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
105 lines
3.0 KiB
C
105 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cbfs.h>
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#include <console/console.h>
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#include <device/dram/ddr3.h>
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#include <gpio.h>
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#include <soc/romstage.h>
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#include <spd.h>
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#include <string.h>
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#include "../gpio.h"
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#include "spd.h"
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
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const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
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const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
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const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
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const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
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const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 };
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int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
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int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
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int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
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int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
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int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
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int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
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int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
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/* Module type */
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printk(BIOS_INFO, "SPD: module type is ");
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switch (spd[SPD_MEMORY_TYPE]) {
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case SPD_MEMORY_TYPE_SDRAM_DDR3:
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printk(BIOS_INFO, "DDR3\n");
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break;
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case SPD_MEMORY_TYPE_LPDDR3_INTEL:
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printk(BIOS_INFO, "LPDDR3\n");
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break;
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default:
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printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]);
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break;
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}
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/* Module Part Number */
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memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN);
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spd_name[SPD_DDR3_PART_LEN] = 0;
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printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
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printk(BIOS_INFO,
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"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
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banks, ranks, rows, cols, capmb);
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printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
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devw, busw);
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if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
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/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
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printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
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capmb / 8 * busw / devw * ranks);
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}
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}
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int mainboard_get_spd_index(void)
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{
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gpio_t spd_gpios[] = {
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GPIO_MEM_CONFIG_0,
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GPIO_MEM_CONFIG_1,
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GPIO_MEM_CONFIG_2,
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GPIO_MEM_CONFIG_3,
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};
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return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
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}
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uintptr_t mainboard_get_spd_data(void)
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{
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char *spd_file;
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size_t spd_file_len;
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int spd_index;
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spd_index = mainboard_get_spd_index();
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printk(BIOS_INFO, "SPD index %d\n", spd_index);
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/* Load SPD data from CBFS */
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spd_file = cbfs_map("spd.bin", &spd_file_len);
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if (!spd_file)
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die("SPD data not found.");
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/* make sure we have at least one SPD in the file. */
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if (spd_file_len < SPD_SIZE_MAX_DDR3)
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die("Missing SPD data.");
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/* Make sure we did not overrun the buffer */
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if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
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printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
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spd_index = 1;
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}
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spd_index *= SPD_SIZE_MAX_DDR3;
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mainboard_print_spd_info((uint8_t *)(spd_file + spd_index));
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return (uintptr_t)(spd_file + spd_index);
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}
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