13831223be
Move i2c SoC related code from early_fch.c to i2c.c TEST=build boards for each SoC Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/i2c.h>
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#include <soc/i2c.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include "chip.h"
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/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
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static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
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I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
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I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
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/* I2C4 is a peripheral device only */
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};
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#if ENV_X86
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/* Preferably keep all the I2C controllers operating in a specific mode together. */
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static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
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{ I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" },
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{ I2C_PERIPHERAL_MODE, APU_I2C4_BASE, "I2C4" } /* Can only be used in peripheral mode */
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};
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#else
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static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
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{ I2C_MASTER_MODE, 0, ""},
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_PERIPHERAL_MODE, 0, "" },
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};
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void i2c_set_bar(unsigned int bus, uintptr_t bar)
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{
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if (bus >= ARRAY_SIZE(i2c_ctrlr)) {
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printk(BIOS_ERR, "i2c index out of bounds: %u.", bus);
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return;
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}
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i2c_ctrlr[bus].bar = bar;
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}
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#endif
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void reset_i2c_peripherals(void)
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{
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const struct soc_amd_picasso_config *cfg = config_of_soc();
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struct soc_i2c_peripheral_reset_info reset_info;
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reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
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reset_info.i2c_scl = i2c_scl_pins;
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reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
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sb_reset_i2c_peripherals(&reset_info);
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}
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void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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{
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/* TODO: Picasso supports I2C RX pad configurations 3.3V, 1.8V and off, so make this
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configurable. */
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const struct i2c_pad_control ctrl = {
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.rx_level = I2C_PAD_RX_3_3V,
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};
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fch_i2c_pad_init(bus, cfg->speed, &ctrl);
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}
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const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
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{
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*num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
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return i2c_ctrlr;
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}
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const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
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{
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const struct soc_amd_picasso_config *config = config_of_soc();
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*num_buses = ARRAY_SIZE(config->i2c);
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return config->i2c;
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}
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