786879777a
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
50 lines
1.5 KiB
Makefile
50 lines
1.5 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2014 Sage Electronic Engineering, LLC.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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ramstage-y += fsp_util.c hob.c
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romstage-y += fsp_util.c hob.c
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ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
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romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
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CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
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ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y)
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cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_HAVE_FSP_BIN),y)
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cbfs-files-y += fsp.bin
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fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
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fsp.bin-position := $(CONFIG_FSP_LOC)
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fsp.bin-type := fsp
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endif
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ifeq ($(CONFIG_ENABLE_MRC_CACHE),y)
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$(obj)/mrc.cache:
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dd if=/dev/zero count=1 \
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bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
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tr '\000' '\377' > $@
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cbfs-files-y += mrc.cache
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mrc.cache-file := $(obj)/mrc.cache
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mrc.cache-position := $(CONFIG_MRC_CACHE_LOC)
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mrc.cache-type := mrc_cache
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endif
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