91ffac8c04
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Fill required FSP-S UPD to call FSP-S API BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
89 lines
1.9 KiB
C
89 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/thermal.h>
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#include <spi-generic.h>
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#include <intelpch/lockdown.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include <timer.h>
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static void pch_handle_sideband(config_t *config)
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{
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}
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static void pch_finalize(void)
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{
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config_t *config = config_of_soc();
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/* TCO Lock down */
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tco_lockdown();
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/* TODO: Add Thermal Configuration */
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pch_handle_sideband(config);
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pmc_clear_pmcon_sts();
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}
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static void tbt_finalize(void)
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{
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int i;
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const struct device *dev;
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/* Disable Thunderbolt PCIe root ports bus master */
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for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
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dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
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if (dev)
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pci_dev_disable_bus_master(dev);
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}
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}
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static void sa_finalize(void)
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{
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if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
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sa_lock_pam();
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}
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static void soc_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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apm_control(APM_CNT_FINALIZE);
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tbt_finalize();
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sa_finalize();
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heci_set_to_d0i3();
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if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
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heci1_disable();
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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/*
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* The purpose of this change is to accommodate more time to push out sending
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* CSE EOP messages at post.
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*/
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);
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