78efc4c36c
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
97 lines
1.5 KiB
Plaintext
97 lines
1.5 KiB
Plaintext
if BOARD_AMD_BIMINI_FAM10
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_ASB2
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select DIMM_DDR3
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select DIMM_REGISTERED
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# TODO: Enable QRANK_DIMM_SUPPORT? Was commented in the Kconfig file,
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# but enabled in the romstage.c file.
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select QRANK_DIMM_SUPPORT
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_AMD_RS780
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select SOUTHBRIDGE_AMD_SB800
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select SUPERIO_ITE_IT8718F
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select HAVE_BUS_CONFIG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select GENERATE_MP_TABLE
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select HAVE_MAINBOARD_RESOURCES
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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select AMDMCT
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select GENERATE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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select RAMINIT_SYSINFO
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select ENABLE_APIC_EXT_ID
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select GFXUMA
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select HAVE_DEBUG_CAR
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default amd/bimini_fam10
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "Bimini (Fam10)"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config MAX_CPUS
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int
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default 8
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config MEM_TRAIN_SEQ
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config IRQ_SLOT_COUNT
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int
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default 11
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config AMD_UCODE_PATCH_FILE
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string
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default "mc_patch_010000b6.h"
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config RAMTOP
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hex
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default 0x2000000
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config HEAP_SIZE
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hex
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default 0xc0000
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config RAMBASE
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hex
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default 0x200000
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endif #BOARD_AMD_BIMINI_FAM10
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