78efc4c36c
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
69 lines
1.0 KiB
Plaintext
69 lines
1.0 KiB
Plaintext
if BOARD_IBM_E326
|
|
|
|
config BOARD_SPECIFIC_OPTIONS # dummy
|
|
def_bool y
|
|
select ARCH_X86
|
|
select CPU_AMD_SOCKET_940
|
|
select NORTHBRIDGE_AMD_AMDK8
|
|
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
|
|
select SOUTHBRIDGE_AMD_AMD8111
|
|
select SOUTHBRIDGE_AMD_AMD8131
|
|
select SUPERIO_NSC_PC87366
|
|
select HAVE_OPTION_TABLE
|
|
select HAVE_PIRQ_TABLE
|
|
select HAVE_MP_TABLE
|
|
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
|
select WAIT_BEFORE_CPUS_INIT
|
|
select BOARD_ROMSIZE_KB_512
|
|
select QRANK_DIMM_SUPPORT
|
|
|
|
config MAINBOARD_DIR
|
|
string
|
|
default ibm/e326
|
|
|
|
config DCACHE_RAM_BASE
|
|
hex
|
|
default 0xcf000
|
|
|
|
config DCACHE_RAM_SIZE
|
|
hex
|
|
default 0x1000
|
|
|
|
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
|
hex
|
|
default 0x0
|
|
|
|
config APIC_ID_OFFSET
|
|
hex
|
|
default 0x0
|
|
|
|
config MAINBOARD_PART_NUMBER
|
|
string
|
|
default "eServer 326"
|
|
|
|
config MAX_CPUS
|
|
int
|
|
default 2
|
|
|
|
config MAX_PHYSICAL_CPUS
|
|
int
|
|
default 2
|
|
|
|
config SB_HT_CHAIN_ON_BUS0
|
|
int
|
|
default 0
|
|
|
|
config HT_CHAIN_END_UNITID_BASE
|
|
hex
|
|
default 0x20
|
|
|
|
config HT_CHAIN_UNITID_BASE
|
|
hex
|
|
default 0x1
|
|
|
|
config IRQ_SLOT_COUNT
|
|
int
|
|
default 12
|
|
|
|
endif # BOARD_IBM_E326
|