78efc4c36c
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
177 lines
2.3 KiB
Plaintext
177 lines
2.3 KiB
Plaintext
if BOARD_MSI_MS9652_FAM10
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_F_1207
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select DIMM_DDR2
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select DIMM_REGISTERED
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_NVIDIA_MCP55
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select MCP55_USE_NIC
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select MCP55_USE_AZA
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select SUPERIO_WINBOND_W83627EHG
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select HAVE_BUS_CONFIG
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select BOARD_ROMSIZE_KB_512
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select RAMINIT_SYSINFO
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select ENABLE_APIC_EXT_ID
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select AMDMCT
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select QRANK_DIMM_SUPPORT
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config MAINBOARD_DIR
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string
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default msi/ms9652_fam10
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config DCACHE_RAM_BASE
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hex
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default 0xc4000
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config DCACHE_RAM_SIZE
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hex
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default 0x0c000
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x04000
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config GENERATE_PIRQ_TABLE
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bool
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default y
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# Define to 0 because the IRQ slot count is
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# determined dynamically for this board.
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config IRQ_SLOT_COUNT
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int
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default 0
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config MAX_CPUS
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int
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default 8
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config LOGICAL_CPUS
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bool
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default y
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config IOAPIC
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bool
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default y
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config SMP
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bool
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default y
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config STACK_SIZE
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hex
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default 0x20000
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config HEAP_SIZE
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hex
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default 0x20000
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config USE_OPTION_TABLE
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bool
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default n
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config MAINBOARD_PART_NUMBER
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string
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default "MS-9652"
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config RAMBASE
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hex
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default 0x200000
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config TTYS0_BAUD
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int
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default 115200
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config TTYS0_BASE
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hex
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default 0x3f8
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config TTYS0_LCS
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int
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default 3
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config DEFAULT_CONSOLE_LOGLEVEL
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int
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default 9
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config MAXIMUM_CONSOLE_LOGLEVEL
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int
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default 9
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config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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bool
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default y
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config CONSOLE_SERIAL8250
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bool
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default y
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config PCI_ROM_RUN
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bool
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default y
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config USBDEBUG
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bool
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default n
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x20
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x00
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config VAR_MTRR_HOLE
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bool
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default n
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config APIC_ID_OFFSET
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hex
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default 0x00
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config LIFT_BSP_APIC_ID
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bool
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default 1
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config RAMTOP
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hex
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default 0x1000000
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config MEM_TRAIN_SEQ
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int
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default 2
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config WAIT_BEFORE_CPUS_INIT
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bool
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default n
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config AMD_UCODE_PATCH_FILE
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string
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default "mc_patch_01000096.h"
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config HT3_SUPPORT
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bool
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default y
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config MCP55_PCI_E_X_0
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int
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default 1
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endif # BOARD_MSI_MS9652_FAM10
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