7922b468b5
The kernel ACPI was not happy with the Add inside a ResourceTemplate (or perhaps within the IO declaration) Instead make a buffer of IO reservations and turn _CRS into a method that updates the buffer depending on the chipset type. This adds an \ISLP() method that checks the chipset LPC device ID to see if it is -LP or -H. It also increases the PM base reservation to 256 bytes and moves both GPIO and PM base to above 0x1000 on -LP chipsets. Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
286 lines
6.1 KiB
Plaintext
286 lines
6.1 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/* Intel Cougar Point PCH support */
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Scope(\)
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{
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// Return TRUE if chipset is LynxPoint-LP
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Method (ISLP, 0, NotSerialized)
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{
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If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) {
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Return (1)
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} else {
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Return (0)
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}
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}
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// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
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OperationRegion(IO_T, SystemIO, 0x800, 0x10)
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Field(IO_T, ByteAcc, NoLock, Preserve)
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{
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Offset(0x8),
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TRP0, 8 // IO-Trap at 0x808
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}
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// PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
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OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0xff)
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Field(PMIO, ByteAcc, NoLock, Preserve)
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{
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Offset(0x20), // GPE0_STS
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, 16,
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GS00, 1, // GPIO00 SCI/Wake Status
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GS01, 1, // GPIO01 SCI/Wake Status
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GS02, 1, // GPIO02 SCI/Wake Status
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GS03, 1, // GPIO03 SCI/Wake Status
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GS04, 1, // GPIO04 SCI/Wake Status
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GS05, 1, // GPIO05 SCI/Wake Status
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GS06, 1, // GPIO06 SCI/Wake Status
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GS07, 1, // GPIO07 SCI/Wake Status
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GS08, 1, // GPIO08 SCI/Wake Status
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GS09, 1, // GPIO09 SCI/Wake Status
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GS10, 1, // GPIO10 SCI/Wake Status
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GS11, 1, // GPIO11 SCI/Wake Status
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GS12, 1, // GPIO12 SCI/Wake Status
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GS13, 1, // GPIO13 SCI/Wake Status
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GS14, 1, // GPIO14 SCI/Wake Status
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GS15, 1, // GPIO15 SCI/Wake Status
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Offset(0x28), // GPE0_EN
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, 16,
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GE00, 1, // GPIO00 SCI/Wake Enable
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GE01, 1, // GPIO01 SCI/Wake Enable
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GE02, 1, // GPIO02 SCI/Wake Enable
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GE03, 1, // GPIO03 SCI/Wake Enable
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GE04, 1, // GPIO04 SCI/Wake Enable
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GE05, 1, // GPIO05 SCI/Wake Enable
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GE06, 1, // GPIO06 SCI/Wake Enable
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GE07, 1, // GPIO07 SCI/Wake Enable
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GE08, 1, // GPIO08 SCI/Wake Enable
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GE09, 1, // GPIO09 SCI/Wake Enable
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GE10, 1, // GPIO10 SCI/Wake Enable
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GE11, 1, // GPIO11 SCI/Wake Enable
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GE12, 1, // GPIO12 SCI/Wake Enable
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GE13, 1, // GPIO13 SCI/Wake Enable
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GE14, 1, // GPIO14 SCI/Wake Enable
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GE15, 1, // GPIO15 SCI/Wake Enable
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Offset(0x42), // General Purpose Control
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, 1, // skip 1 bit
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GPEC, 1, // SWGPE_CTRL
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}
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// GPIO IO mapped registers (0x1f.0 reg 0x48.l)
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OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
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Field(GPIO, ByteAcc, NoLock, Preserve)
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{
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Offset(0x00), // GPIO Use Select
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GU00, 8,
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GU01, 8,
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GU02, 8,
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GU03, 8,
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Offset(0x04), // GPIO IO Select
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GIO0, 8,
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GIO1, 8,
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GIO2, 8,
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GIO3, 8,
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Offset(0x0c), // GPIO Level
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GL00, 1,
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GP01, 1,
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GP02, 1,
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GP0e, 1,
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GP04, 1,
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GP05, 1,
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GP06, 1,
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GP07, 1,
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GP08, 1,
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GP09, 1,
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GP10, 1,
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GP11, 1,
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GP12, 1,
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GP13, 1,
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GP14, 1,
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GP15, 1,
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GP16, 1,
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GP17, 1,
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GP18, 1,
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GP19, 1,
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GP20, 1,
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GP21, 1,
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GP22, 1,
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GP23, 1,
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GP24, 1,
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GP25, 1,
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GP26, 1,
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GP27, 1,
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GP28, 1,
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GP29, 1,
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GP30, 1,
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GP31, 1,
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Offset(0x18), // GPIO Blink
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GB00, 8,
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GB01, 8,
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GB02, 8,
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GB03, 8,
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Offset(0x2c), // GPIO Invert
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GIV0, 8,
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GIV1, 8,
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GIV2, 8,
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GIV3, 8,
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Offset(0x30), // GPIO Use Select 2
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GU04, 8,
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GU05, 8,
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GU06, 8,
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GU07, 8,
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Offset(0x34), // GPIO IO Select 2
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GIO4, 8,
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GIO5, 8,
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GIO6, 8,
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GIO7, 8,
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Offset(0x38), // GPIO Level 2
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GP32, 1,
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GP33, 1,
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GP34, 1,
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GP35, 1,
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GP36, 1,
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GP37, 1,
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GP38, 1,
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GP39, 1,
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GP40, 1,
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GP41, 1,
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GP42, 1,
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GP43, 1,
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GP44, 1,
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GP45, 1,
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GP46, 1,
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GP47, 1,
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GP48, 1,
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GP49, 1,
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GP50, 1,
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GP51, 1,
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GP52, 1,
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GP53, 1,
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GP54, 1,
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GP55, 1,
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GP56, 1,
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GP57, 1,
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GP58, 1,
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GP59, 1,
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GP60, 1,
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GP61, 1,
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GP62, 1,
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GP63, 1,
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Offset(0x40), // GPIO Use Select 3
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GU08, 8,
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GU09, 4,
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Offset(0x44), // GPIO IO Select 3
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GIO8, 8,
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GIO9, 4,
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Offset(0x48), // GPIO Level 3
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GP64, 1,
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GP65, 1,
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GP66, 1,
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GP67, 1,
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GP68, 1,
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GP69, 1,
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GP70, 1,
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GP71, 1,
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GP72, 1,
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GP73, 1,
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GP74, 1,
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GP75, 1,
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}
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// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
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OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
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Field(RCRB, DWordAcc, Lock, Preserve)
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{
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Offset(0x0000), // Backbone
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Offset(0x1000), // Chipset
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Offset(0x3000), // Legacy Configuration Registers
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Offset(0x3404), // High Performance Timer Configuration
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HPAS, 2, // Address Select
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, 5,
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HPTE, 1, // Address Enable
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Offset(0x3418), // FD (Function Disable)
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, 1, // Reserved
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PCID, 1, // PCI bridge disable
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SA1D, 1, // SATA1 disable
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SMBD, 1, // SMBUS disable
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HDAD, 1, // Azalia disable
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, 8, // Reserved
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EH2D, 1, // EHCI #2 disable
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LPBD, 1, // LPC bridge disable
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EH1D, 1, // EHCI #1 disable
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RP1D, 1, // Root Port 1 disable
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RP2D, 1, // Root Port 2 disable
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RP3D, 1, // Root Port 3 disable
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RP4D, 1, // Root Port 4 disable
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RP5D, 1, // Root Port 5 disable
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RP6D, 1, // Root Port 6 disable
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RP7D, 1, // Root Port 7 disable
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RP8D, 1, // Root Port 8 disable
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TTRD, 1, // Thermal sensor registers disable
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SA2D, 1, // SATA2 disable
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Offset(0x3428), // FD2 (Function Disable 2)
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BDFD, 1, // Display BDF
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ME1D, 1, // ME Interface 1 disable
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ME2D, 1, // ME Interface 2 disable
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IDRD, 1, // IDE redirect disable
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KTCT, 1, // Keyboard Text redirect disable
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}
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}
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// High Definition Audio (Azalia) 0:1b.0
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#include "audio.asl"
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// PCI Express Ports 0:1c.x
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#include "pcie.asl"
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// USB 0:1d.0 and 0:1a.0
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#include "usb.asl"
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// LPC Bridge 0:1f.0
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#include "lpc.asl"
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// SATA 0:1f.2, 0:1f.5
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#include "sata.asl"
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// SMBus 0:1f.3
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#include "smbus.asl"
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Method (_OSC, 4)
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{
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/* Check for proper GUID */
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If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
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{
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/* Let OS control everything */
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Return (Arg3)
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}
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Else
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{
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/* Unrecognized UUID */
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CreateDWordField (Arg3, 0, CDW1)
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Or (CDW1, 4, CDW1)
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Return (Arg3)
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}
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}
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