2ad74deb2a
Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
94 lines
2.9 KiB
C
94 lines
2.9 KiB
C
/*
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <libpayload.h>
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#include <pci.h>
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static int find_on_bus(int bus, unsigned short vid, unsigned short did,
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pcidev_t * dev)
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{
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int devfn;
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u32 val;
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unsigned char hdr;
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for (devfn = 0; devfn < 0x100; devfn++) {
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int func = devfn & 0x7;
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int slot = (devfn >> 3) & 0x1f;
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val = pci_read_config32(PCI_DEV(bus, slot, func),
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REG_VENDOR_ID);
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if (val == 0xffffffff || val == 0x00000000 ||
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val == 0x0000ffff || val == 0xffff0000)
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continue;
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if (val == ((did << 16) | vid)) {
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*dev = PCI_DEV(bus, slot, func);
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return 1;
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}
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hdr = pci_read_config8(PCI_DEV(bus, slot, func),
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REG_HEADER_TYPE);
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hdr &= 0x7F;
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if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) {
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unsigned int busses;
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busses = pci_read_config32(PCI_DEV(bus, slot, func),
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REG_PRIMARY_BUS);
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busses = (busses >> 8) & 0xFF;
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/* Avoid recursion if the new bus is the same as
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* the old bus (insert lame The Who joke here) */
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if ((busses != bus) &&
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find_on_bus(busses, vid, did, dev))
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return 1;
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}
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}
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return 0;
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}
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int pci_find_device(u16 vid, u16 did, pcidev_t * dev)
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{
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return find_on_bus(0, vid, did, dev);
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}
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u32 pci_read_resource(pcidev_t dev, int bar)
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{
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return pci_read_config32(dev, 0x10 + (bar * 4));
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}
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void pci_set_bus_master(pcidev_t dev)
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{
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u16 val = pci_read_config16(dev, REG_COMMAND);
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val |= REG_COMMAND_BM;
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pci_write_config16(dev, REG_COMMAND, val);
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}
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