79d7f6b5fc
Now, Super I/O GPIOs can also be controlled directly through access to I/O registers. VLDN 108 and specific I/O port from a range <100h; ff8h> may be enabled in mainboard devicetree. Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
248 lines
6.5 KiB
C
248 lines
6.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pnp.h>
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#include <device/device.h>
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#include <superio/conf_mode.h>
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#include "nct5104d.h"
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#include "chip.h"
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static void set_irq_trigger_type(struct device *dev, bool trig_level)
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{
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u8 reg10, reg11, reg26;
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//Before accessing CR10 OR CR11 Bit 4 in CR26 must be set to 1
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reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
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reg26 |= CR26_LOCK_REG;
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pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
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switch (dev->path.pnp.device) {
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//SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5
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case NCT5104D_SP1:
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reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
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if (trig_level)
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reg10 |= (1 << 5);
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else
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reg10 &= ~(1 << 5);
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pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
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break;
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//SP2 (UARTB) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 4
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case NCT5104D_SP2:
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reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
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if (trig_level)
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reg10 |= (1 << 4);
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else
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reg10 &= ~(1 << 4);
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pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
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break;
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//SP3 (UARTC) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 5
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case NCT5104D_SP3:
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reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
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if (trig_level)
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reg11 |= (1 << 5);
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else
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reg11 &= ~(1 << 5);
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pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
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break;
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//SP4 (UARTD) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 4
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case NCT5104D_SP4:
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reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
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if (trig_level)
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reg11 |= (1 << 4);
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else
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reg11 &= ~(1 << 4);
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pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
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break;
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default:
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break;
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}
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//Clear access control register
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reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
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reg26 &= ~CR26_LOCK_REG;
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pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
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}
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static void route_pins_to_uart(struct device *dev, bool to_uart)
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{
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u8 reg;
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reg = pnp_read_config(dev, 0x1c);
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switch (dev->path.pnp.device) {
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case NCT5104D_SP3:
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case NCT5104D_GPIO0:
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/* Route pins 33 - 40. */
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if (to_uart)
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reg |= (1 << 3);
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else
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reg &= ~(1 << 3);
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break;
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case NCT5104D_SP4:
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case NCT5104D_GPIO1:
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/* Route pins 41 - 48. */
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if (to_uart)
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reg |= (1 << 2);
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else
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reg &= ~(1 << 2);
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break;
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default:
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break;
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}
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pnp_write_config(dev, 0x1c, reg);
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}
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static void reset_gpio_default_in(struct device *dev)
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{
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pnp_set_logical_device(dev);
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/* Soft reset GPIOs to default state: IN */
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switch (dev->path.pnp.device) {
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case NCT5104D_GPIO0:
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pnp_write_config(dev, NCT5104D_GPIO0_IO, 0xFF);
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break;
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case NCT5104D_GPIO1:
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pnp_write_config(dev, NCT5104D_GPIO1_IO, 0xFF);
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break;
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case NCT5104D_GPIO6:
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pnp_write_config(dev, NCT5104D_GPIO6_IO, 0xFF);
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break;
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default:
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break;
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}
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}
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static void reset_gpio_default_od(struct device *dev)
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{
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struct device *gpio0, *gpio1, *gpio6;
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gpio0 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO0);
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gpio1 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO1);
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gpio6 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO6);
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pnp_set_logical_device(dev);
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/* Soft reset GPIOs to default state: Open-drain */
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if (gpio0 && gpio0->enabled)
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pnp_write_config(dev, NCT5104D_GPIO0_PP_OD, 0xFF);
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if (gpio1 && gpio1->enabled)
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pnp_write_config(dev, NCT5104D_GPIO1_PP_OD, 0xFF);
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if (gpio6 && gpio6->enabled)
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pnp_write_config(dev, NCT5104D_GPIO6_PP_OD, 0xFF);
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}
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static void disable_gpio_io_port(struct device *dev)
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{
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struct device *gpio0, *gpio1, *gpio6;
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/*
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* Since UARTC and UARTD share pins with GPIO0 and GPIO1 and the
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* GPIO/UART can be selected via Kconfig, check whether at least one of
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* GPIOs is enabled and if yes keep the GPIO IO VLDN enabled. If no
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* GPIOs are enabled, disable the VLDN in order to protect from invalid
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* devicetree + Kconfig settings.
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*/
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gpio0 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO0);
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gpio1 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO1);
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gpio6 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO6);
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if (!((gpio0 && gpio0->enabled) || (gpio1 && gpio1->enabled) ||
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(gpio6 && gpio6->enabled))) {
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dev->enabled = 0;
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printk(BIOS_WARNING, "WARNING: GPIO IO port configured,"
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" but no GPIO enabled. Disabling...");
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}
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}
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static void nct5104d_init(struct device *dev)
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{
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struct superio_nuvoton_nct5104d_config *conf = dev->chip_info;
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if (!dev->enabled)
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return;
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pnp_enter_conf_mode(dev);
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switch (dev->path.pnp.device) {
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case NCT5104D_SP1:
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case NCT5104D_SP2:
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set_irq_trigger_type(dev, conf->irq_trigger_type != 0);
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break;
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case NCT5104D_SP3:
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case NCT5104D_SP4:
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route_pins_to_uart(dev, true);
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set_irq_trigger_type(dev, conf->irq_trigger_type != 0);
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break;
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case NCT5104D_GPIO0:
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case NCT5104D_GPIO1:
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route_pins_to_uart(dev, false);
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reset_gpio_default_in(dev);
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break;
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case NCT5104D_GPIO6:
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reset_gpio_default_in(dev);
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break;
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case NCT5104D_GPIO_PP_OD:
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reset_gpio_default_od(dev);
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break;
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case NCT5104D_GPIO_IO:
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disable_gpio_io_port(dev);
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break;
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default:
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break;
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}
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pnp_exit_conf_mode(dev);
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = nct5104d_init,
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.ops_pnp_mode = &pnp_conf_mode_8787_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ NULL, NCT5104D_FDC, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, NCT5104D_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, NCT5104D_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, NCT5104D_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, NCT5104D_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, NCT5104D_GPIO_WDT},
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{ NULL, NCT5104D_GPIO0},
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{ NULL, NCT5104D_GPIO1},
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{ NULL, NCT5104D_GPIO6},
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{ NULL, NCT5104D_GPIO_PP_OD},
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{ NULL, NCT5104D_GPIO_IO, PNP_IO0, 0x07f8, },
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{ NULL, NCT5104D_PORT80},
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_nuvoton_nct5104d_ops = {
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CHIP_NAME("Nuvoton NCT5104D Super I/O")
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.enable_dev = enable_dev,
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};
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