Select 'HAVE_INTEL_FSP_REPO' so that the FSP binary from the FSP repository is used by default. Also, use the FSP headers from the FSP repository instead. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I0c1bcb07ed0f73e1d5ada5f6f16b84816c4ef3d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55229 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
219 lines
4.9 KiB
Plaintext
219 lines
4.9 KiB
Plaintext
config SOC_INTEL_ELKHARTLAKE
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bool
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help
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Intel Elkhartlake support
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if SOC_INTEL_ELKHARTLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_ALL_STAGES_X86_32
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CPU_INTEL_COMMON
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_SUPPORTS_PM_TIMER_EMULATION
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select FSP_COMPRESS_FSP_S_LZ4
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select FSP_M_XIP
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select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select IOAPIC
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select MP_SERVICES_PPI_V1
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select MRC_SETTINGS_PROTECT
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select PARALLEL_MP_AP_WORK
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select MICROCODE_BLOB_UNDISCLOSED
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select PLATFORM_USES_FSP2_1
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select REG_SCRIPT
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select PMC_LOW_POWER_MODE_PROGRAM
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
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select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
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select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SCS
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_RESET
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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select UDK_202005_BINDING
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select DISPLAY_FSP_VERSION_INFO
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select HAVE_INTEL_FSP_REPO
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config MAX_CPUS
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int
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default 4
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config DCACHE_RAM_BASE
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default 0xfef00000
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config DCACHE_RAM_SIZE
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default 0xc0000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x30000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages. In the case of FSP_USES_CB_STACK default value will be
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sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
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config FSP_TEMP_RAM_SIZE
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hex
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default 0x40000
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help
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The amount of anticipated heap usage in CAR by FSP.
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Refer to Platform FSP integration guide document to know
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the exact FSP requirement for Heap setup.
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config IFD_CHIPSET
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string
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default "ehl"
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config IED_REGION_SIZE
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hex
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default 0x0
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config HEAP_SIZE
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hex
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default 0x8000
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config MAX_ROOT_PORTS
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int
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default 7
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config MAX_SATA_PORTS
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int
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default 2
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config MAX_PCIE_CLOCK_SRC
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int
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default 6
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config SMM_TSEG_SIZE
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hex
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default 0x1000000
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config SMM_RESERVED_SIZE
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hex
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default 0x200000
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config MMCONF_BASE_ADDRESS
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default 0xc0000000
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config CPU_BCLK_MHZ
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int
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default 100
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config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
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int
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default 120
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config CPU_XTAL_HZ
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default 38400000
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 133
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 3
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config SOC_INTEL_I2C_DEV_MAX
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int
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default 8
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config SOC_INTEL_UART_DEV_MAX
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int
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default 3
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config CONSOLE_UART_BASE_ADDRESS
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hex
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default 0xfe042000
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depends on INTEL_LPSS_UART_FOR_CONSOLE
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# Clock divider parameters for 115200 baud rate
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# Baudrate = (UART source clcok * M) /(N *16)
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# EHL UART source clock: 100MHz
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x30
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0xc35
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config VBOOT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config CBFS_SIZE
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hex
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default 0x200000
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config FSP_HEADER_PATH
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default "3rdparty/fsp/ElkhartLakeFspBinPkg/Include/"
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config FSP_FD_PATH
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string
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depends on FSP_USE_REPO
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default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSPRel.bin"
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config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT
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int "Debug Consent for EHL"
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# USB DBC is more common for developers so make this default to 3 if
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# SOC_INTEL_DEBUG_CONSENT=y
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default 3 if SOC_INTEL_DEBUG_CONSENT
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default 0
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help
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This is to control debug interface on SOC.
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Setting non-zero value will allow to use DBC or DCI to debug SOC.
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PlatformDebugConsent in FspmUpd.h has the details.
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Desired platform debug type are
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0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
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3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
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6:Enable (2-wire DCI OOB), 7:Manual
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x1400
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endif
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