7a95575b85
Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38255 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include <device/smbus_host.h>
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#include "i82371eb.h"
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void i82371eb_early_init(void)
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{
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enable_smbus();
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enable_pm();
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}
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void enable_smbus(void)
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{
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pci_devfn_t dev;
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u8 reg8;
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u16 reg16;
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/* Get the SMBus/PM device of the 82371AB/EB/MB. */
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
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/* Set the SMBus I/O base. */
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pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
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/* Enable the SMBus controller host interface. */
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reg8 = pci_read_config8(dev, SMBHSTCFG);
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reg8 |= SMB_HST_EN;
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pci_write_config8(dev, SMBHSTCFG, reg8);
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/* Enable access to the SMBus I/O space. */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_IO;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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smbus_host_reset(SMBUS_IO_BASE);
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printk(BIOS_DEBUG, "SMBus controller enabled\n");
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}
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int smbus_read_byte(u8 device, u8 address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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