7b42811fa5
This commit follows up on commit 2e464cf3 with Change-Id
I61fb3b01ff15ba2da2ee938addfa630c282c9870.
Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
406 lines
12 KiB
C
406 lines
12 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
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#define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
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#include <arch/acpi.h>
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/* SOC types */
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#define SOC_TYPE_RANGELEY 0x1F
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/*
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* It does not matter where we put the SMBus I/O base, as long as we
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* keep it consistent and don't interfere with other devices. Stage2
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* will relocate this anyways.
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* Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
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* again. But handling static BARs is a generic problem that should be
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* solved in the device allocator.
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*/
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/* Southbridge internal device IO BARs (Set to match FSP settings) */
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#define SMBUS_IO_BASE 0xefa0
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#define SMBUS_SLAVE_ADDR 0x24
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#define DEFAULT_GPIOBASE 0x0500
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#define DEFAULT_ABASE 0x0400
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/* Southbridge internal device MEM BARs (Set to match FSP settings) */
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#define DEFAULT_IBASE 0xfed08000
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#define DEFAULT_PBASE 0xfed03000
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#include <southbridge/intel/common/rcba.h>
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#ifndef __ACPI__
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#define DEBUG_PERIODIC_SMIS 0
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#if defined(__SMM__) && !defined(__ASSEMBLER__)
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void intel_soc_finalize_smm(void);
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#endif
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#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
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#if !defined(__PRE_RAM__) && !defined(__SMM__)
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#include "chip.h"
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int soc_silicon_revision(void);
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int soc_silicon_type(void);
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int soc_silicon_supported(int type, int rev);
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void soc_enable(struct device *dev);
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void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
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#if IS_ENABLED(CONFIG_ELOG)
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void soc_log_state(void);
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#endif
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#else
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void enable_smbus(void);
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void enable_usb_bar(void);
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int smbus_read_byte(unsigned device, unsigned address);
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int early_spi_read(u32 offset, u32 size, u8 *buffer);
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void rangeley_sb_early_initialization(void);
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#endif
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#endif
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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#define SOC_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
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#define PCIE_DEV_SLOT0 1
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#define PCIE_DEV_SLOT1 2
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#define PCIE_DEV_SLOT2 3
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#define PCIE_DEV_SLOT3 4
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/* PCI Configuration Space (D31:F0): LPC */
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#define SOC_LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0)
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/* Southbridge IO BARs */
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#define ABASE 0x40 /* IO BAR */
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#define PBASE 0x44 /* MEM BAR */
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#define GBASE 0x48 /* IO BAR */
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#define IOBASE 0x4C /* MEM BAR */
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#define IBASE 0x50 /* MEM BAR */
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#define SBASE 0x54 /* MEM BAR */
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#define MPBASE 0x58 /* MEM BAR */
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#define SET_BAR_ENABLE 0x02
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/* Rangeley ILB defines */
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#define ILB_ACTL 0
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#define ILB_PIRQA_ROUT 0x8
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#define ILB_PIRQB_ROUT 0x9
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#define ILB_PIRQC_ROUT 0xA
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#define ILB_PIRQD_ROUT 0xB
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#define ILB_PIRQE_ROUT 0xC
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#define ILB_PIRQF_ROUT 0xD
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#define ILB_PIRQG_ROUT 0xE
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#define ILB_PIRQH_ROUT 0xF
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#define ILB_SERIRQ_CNTL 0x10
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#define ILB_IR00 0x20
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#define ILB_IR01 0x22
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#define ILB_IR02 0x24
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#define ILB_IR03 0x26
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#define ILB_IR04 0x28
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#define ILB_IR05 0x2A
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#define ILB_IR06 0x2C
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#define ILB_IR07 0x2E
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#define ILB_IR08 0x30
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#define ILB_IR09 0x32
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#define ILB_IR10 0x34
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#define ILB_IR11 0x36
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#define ILB_IR12 0x38
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#define ILB_IR13 0x3A
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#define ILB_IR14 0x3C
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#define ILB_IR15 0x3E
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#define ILB_IR16 0x40
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#define ILB_IR17 0x42
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#define ILB_IR18 0x44
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#define ILB_IR19 0x46
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#define ILB_IR20 0x48
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#define ILB_IR21 0x4A
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#define ILB_IR22 0x4C
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#define ILB_IR23 0x4E
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#define ILB_IR24 0x50
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#define ILB_IR25 0x52
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#define ILB_IR26 0x54
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#define ILB_IR27 0x56
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#define ILB_IR28 0x58
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#define ILB_IR29 0x5A
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#define ILB_IR30 0x5C
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#define ILB_IR31 0x5E
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#define ILB_OIC 0x60
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/* PCI Configuration Space (D31:F2/5) */
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#define SOC_SATA_DEV PCI_DEV(0, 0x17, 0)
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#define SOC_SATA2_DEV PCI_DEV(0, 0x18, 0)
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#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
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#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
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#define SATA_SP 0xd0 /* Scratchpad */
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#define SATA_MAP 0x90
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#define SATA_PSC 0x92
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/* SATA IOBP Registers */
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#define SATA_IOBP_SP0G3IR 0xea000151
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#define SATA_IOBP_SP1G3IR 0xea000051
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/* PCI Configuration Space (D31:F3): SMBus */
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#define SOC_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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#define SMB_RCV_SLVA 0x09
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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/* Root Port configuration space hide */
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#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
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/* Get the function number assigned to a Root Port */
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#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
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/* Set the function number for a Root Port */
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#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
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/* Root Port function number mask */
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#define RPFN_FNMASK(port) (7 << ((port) * 4))
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#define NOINT 0
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#define INTA 1
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#define INTB 2
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#define INTC 3
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#define INTD 4
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#define DIR_IDR 12 /* Interrupt D Pin Offset */
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#define DIR_ICR 8 /* Interrupt C Pin Offset */
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#define DIR_IBR 4 /* Interrupt B Pin Offset */
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#define DIR_IAR 0 /* Interrupt A Pin Offset */
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#define PIRQA 0
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#define PIRQB 1
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#define PIRQC 2
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#define PIRQD 3
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#define PIRQE 4
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#define PIRQF 5
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#define PIRQG 6
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#define PIRQH 7
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/* IO Buffer Programming */
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#define IOBPIRI 0x2330
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#define IOBPD 0x2334
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#define IOBPS 0x2338
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#define IOBPS_RW_BX ((1 << 9)|(1 << 10))
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#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
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#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
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#define DIR_ROUTE(x,a,b,c,d) \
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RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
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((b) << DIR_IBR) | ((a) << DIR_IAR))
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/* PBASE Registers */
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#define PMC_CFG 0x08
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#define SPS (1 << 5)
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#define NO_REBOOT (1 << 4)
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#define SX_ENT_TO_EN (1 << 3)
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#define TIMING_T581 (1 << 0)
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#define GEN_PMCON1 0x20
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# define DISB (1 << 23)
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# define MEM_SR (1 << 21)
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# define SRS (1 << 20)
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# define CTS (1 << 19)
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# define MS4V (1 << 18)
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# define PWR_FLR (1 << 16)
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# define PME_B0_S5_DIS (1 << 15)
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# define SUS_PWR_FLR (1 << 14)
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# define WOL_EN_OVRD (1 << 13)
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# define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
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# define GEN_RST_STS (1 << 9)
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# define RPS (1 << 2)
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# define AFTERG3_EN (1 << 0)
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/* Function Disable PBASE + 0x34 */
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#define PBASE_FUNC_DIS 0x34
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#define PBASE_DISABLE_QUICKASSIST (1 << 0)
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#define PBASE_DISABLE_GBE(x) (1 << (12 + x))
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#define PBASE_DISABLE_SATA2 (1 << 22)
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#define PBASE_DISABLE_EHCI (1 << 23)
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#define PBASE_DISABLE_SATA3 (1 << 23)
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/* GPIOBASE */
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#define GPIO_SC_USE_SEL 0x00
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#define GPIO_SC_IO_SEL 0x04
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#define GPIO_SC_GP_LVL 0x08
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#define GPIO_SC_TPE 0x0c
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#define GPIO_SC_TNE 0x10
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#define GPIO_SC_TS 0x14
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#define GPIO_SUS_USE_SEL 0x80
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#define GPIO_SUS_IO_SEL 0x84
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#define GPIO_SUS_GP_LVL 0x88
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#define GPIO_SUS_TPE 0x8c
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#define GPIO_SUS_TNE 0x90
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#define GPIO_SUS_TS 0x94
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#define GPIO_SUS_WE 0x98
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/* IOBASE */
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#define CFIO_PAD_CONF0 0x00
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#define CFIO_PAD_CONF1 0x04
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#define CFIO_PAD_VAL 0x08
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#define CFIO_PAD_DFT 0x0C
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/* ACPI BASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define PROC_CNT 0x10
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#define LV2 0x14
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#define LV3 0x15
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#define LV4 0x16
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#define PM2_CNT 0x50 // mobile only
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#define GPE0_STS 0x20
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#define PME_B0_STS (1 << 13)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define RI_STS (1 << 8)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_EN 0x28
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#define PME_B0_EN (1 << 13)
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#define PME_EN (1 << 11)
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#define TCOSCI_EN (1 << 6)
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#define SMI_EN 0x30
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#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
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#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
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#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
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#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
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#define MCSMI_EN (1 << 11) // Trap microcontroller range access
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#define BIOS_RLS (1 << 7) // asserts SCI on bit set
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#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
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#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
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#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
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#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
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#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
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#define EOS (1 << 1) // End of SMI (deassert SMI#)
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#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
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#define SMI_STS 0x34
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#define ALT_GP_SMI_EN 0x38
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#define ALT_GP_SMI_STS 0x3a
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#define GPE_CNTL 0x42
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#define DEVACT_STS 0x44
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#define PM2A_CNT_BLK 0x50
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#define SS_CNT 0x50
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#define C3_RES 0x54
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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#define TCO1_CNT 0x68
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#define TCO_TMR_HALT (1 << 11)
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#define TCO_LOCK (1 << 12)
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/*
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* SPI Opcode Menu setup for SPIBAR lockdown
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* should support most common flash chips.
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*/
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#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
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#define SPI_OPTYPE_0 0x01 /* Write, no address */
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#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
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#define SPI_OPTYPE_1 0x03 /* Write, address required */
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#define SPI_OPMENU_2 0x03 /* READ: Read Data */
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#define SPI_OPTYPE_2 0x02 /* Read, address required */
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#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
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#define SPI_OPTYPE_3 0x00 /* Read, no address */
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#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
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#define SPI_OPTYPE_4 0x03 /* Write, address required */
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#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
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#define SPI_OPTYPE_5 0x00 /* Read, no address */
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#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
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#define SPI_OPTYPE_6 0x03 /* Write, address required */
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#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
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#define SPI_OPTYPE_7 0x02 /* Read, address required */
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#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
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(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
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#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
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#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
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(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
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(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
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#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
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#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
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#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
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#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
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#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
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#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
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#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
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#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
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#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
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#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
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#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
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#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
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#define SPIBAR_FADDR 0x08 /* SPI flash address */
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#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
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/* HPET Registers - Base is set in hardware to 0xFED00000 */
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#define HPET_GCID 0xFED00000 /* General Capabilities and ID */
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#define HPET_GCFG 0xFED00010 /* General Configuration */
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#define HPET_GIS 0xFED00020 /* General Interrupt Status */
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#define HPET_MCV 0xFED000F0 /* Main Counter Value */
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#define HPET_T0C 0xFED00100 /* Timer 0 Configuration and Capabilities */
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#define HPET_T0CV_L 0xFED00108 /* Lower Timer 0 Comparator Value */
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#define HPET_T0CV_U 0xFED0010C /* Upper Timer 0 Comparator Value */
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#define HPET_T1C 0xFED00120 /* Timer 1 Configuration and Capabilities */
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#define HPET_T1CV 0xFED00128 /* Timer 1 Comparator Value */
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#define HPET_T2C 0xFED00140 /* Timer 2 Configuration and Capabilities */
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#define HPET_T2CV 0xFED00148 /* Timer 2 Comparator Value */
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#endif /* __ACPI__ */
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#endif /* SOUTHBRIDGE_INTEL_RANGELEY_SOC_H */
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