7c0c64e103
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
43 lines
1.5 KiB
C
Executable File
43 lines
1.5 KiB
C
Executable File
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _CIMX_SB900_CHIP_H_
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#define _CIMX_SB900_CHIP_H_
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extern struct chip_operations southbridge_amd_cimx_sb900_ops;
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/*
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* configuration set in mainboard/devicetree.cb
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* boot_switch_sata_ide:
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* 0 -set SATA as primary, PATA(IDE) as secondary.
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* 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
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* gpp_configuration - The configuration of General Purpose Port A/B/C/D
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* 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
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* 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
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* 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
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* 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
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*/
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struct southbridge_amd_cimx_sb900_config
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{
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u32 boot_switch_sata_ide : 1;
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u8 gpp_configuration;
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};
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#endif /* _CIMX_SB900_CHIP_H_ */
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