7d86f34398
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
25 lines
667 B
Plaintext
25 lines
667 B
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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config SOC_EXAMPLE_MIN86
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bool
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select ARCH_X86
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select NO_MONOTONIC_TIMER
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select NO_ECAM_MMCONF_SUPPORT
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select UNKNOWN_TSC_RATE
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help
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This example SoC code along with the example/min86 mainboard
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should serve as a minimal example how a buildable x86 SoC code
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base can look like.
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This can serve, for instance, as a basis to add new SoCs to
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coreboot. Starting with a buildable commit should help with
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the review of the actual code, and also avoid any regressions
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when common coreboot code changes.
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if SOC_EXAMPLE_MIN86
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config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
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default 0x100
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endif
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