aedbfc8f09
Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
118 lines
2.3 KiB
Plaintext
118 lines
2.3 KiB
Plaintext
config SOC_INTEL_COMMON
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bool
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help
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common code for Intel SOCs
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if SOC_INTEL_COMMON
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config CACHE_MRC_SETTINGS
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bool "Save cached MRC settings"
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default n
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config SOC_INTEL_COMMON_SPI_PROTECT
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bool
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default n
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if CACHE_MRC_SETTINGS
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config MRC_SETTINGS_CACHE_BASE
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hex
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default 0xfffe0000
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config MRC_SETTINGS_CACHE_SIZE
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hex
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default 0x10000
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config MRC_SETTINGS_PROTECT
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bool "Enable protection on MRC settings"
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default n
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endif # CACHE_MRC_SETTINGS
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config DISPLAY_MTRRS
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bool "MTRRs: Display the MTRR settings"
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default n
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config DISPLAY_SMM_MEMORY_MAP
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bool "SMM: Display the SMM memory map"
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default n
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config SOC_INTEL_COMMON_RESET
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bool
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default n
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config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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bool
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default n
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config ACPI_CONSOLE
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bool
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default n
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help
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Provide a mechanism for serial console based ACPI debug.
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config SOC_INTEL_COMMON_LPSS_I2C
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bool
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default n
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help
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This driver supports the Intel Low Power Subsystem (LPSS) I2C
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controllers that are based on Synopsys DesignWare IP.
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config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
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int
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depends on SOC_INTEL_COMMON_LPSS_I2C
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help
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The clock speed that the I2C controller is running at, in MHz.
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No default is set here as this is an SOC-specific value and must
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be provided by the SOC when it selects this driver.
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config SOC_INTEL_COMMON_LPSS_I2C_DEBUG
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bool "Enable debug output for LPSS I2C transactions"
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default n
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depends on SOC_INTEL_COMMON_LPSS_I2C
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help
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Enable debug output for I2C transactions. This can be useful
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when debugging I2C drivers.
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config MMA
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bool "enable MMA (Memory Margin Analysis) support"
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default n
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help
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Set this option to y to enable MMA (Memory Margin Analysis) support
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config MMA_BLOBS_PATH
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string "Path to MMA blobs"
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depends on MMA
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma"
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config ADD_VBT_DATA_FILE
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bool "Add a Video Bios Table (VBT) binary to CBFS"
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help
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Add a VBT file data file to CBFS. The VBT describes the integrated
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GPU and connections, and is needed by FSP in order to initialize the
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display.
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config VBT_FILE
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string "VBT binary path and filename"
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depends on ADD_VBT_DATA_FILE
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help
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The path and filename of the VBT binary.
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config SOC_INTEL_COMMON_GFX_OPREGION
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bool
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default n
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config SOC_INTEL_COMMON_SMI
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bool
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default n
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config SOC_INTEL_COMMON_ACPI
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bool
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default n
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config SOC_INTEL_COMMON_NHLT
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bool
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default n
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endif # SOC_INTEL_COMMON
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