220 lines
6.6 KiB
Plaintext
220 lines
6.6 KiB
Plaintext
chip soc/intel/alderlake
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register "common_soc_config" = "{
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# ACPI (soc/intel/alderlake/acpi.c)
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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register "s0ix_enable" = "1"
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# FSP Memory (soc/intel/alderlake/romstage/fsp_params.c)
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/alderlake/fsp_params.c)
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# FIVR configuration
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# Read EXT_RAIL_CONFIG to determine bitmaps
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# sudo devmem2 0xfe0011b8
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# 0x0
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# Read EXT_V1P05_VR_CONFIG
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# sudo devmem2 0xfe0011c0
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# 0x1a42000
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# Read EXT_VNN_VR_CONFIG0
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# sudo devmem2 0xfe0011c4
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# 0x1a42000
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# TODO: v1p05 voltage and vnn icc max?
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = 0,
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.vnn_enable_bitmap = 0,
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.v1p05_supported_voltage_bitmap = 0,
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.vnn_supported_voltage_bitmap = 0,
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.v1p05_icc_max_ma = 500,
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.vnn_sx_voltage_mv = 1050,
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}"
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# Thermal
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register "tcc_offset" = "10"
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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# PM Util (soc/intel/alderlake/pmutil.c)
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# GPE configuration
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register "pmc_gpe0_dw0" = "PMC_GPP_R"
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register "pmc_gpe0_dw1" = "PMC_GPP_B"
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register "pmc_gpe0_dw2" = "PMC_GPP_D"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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#From CPU EDS(TODO)
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device ref system_agent on end
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device ref pcie5 on
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# PCIe PEG2 x8, Clock 3 (DGPU)
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register "cpu_pcie_rp[CPU_RP(2)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip drivers/gfx/nvidia
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device pci 00.0 on end # VGA controller
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device pci 00.1 on end # Audio device
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device pci 00.2 on end # USB xHCI Host controller
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device pci 00.3 on end # USB Type-C UCSI controller
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end
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end
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device ref igpu on
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# DDIA is eDP
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register "ddi_portA_config" = "1"
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register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
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end
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device ref pcie4_0 on
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# PCIe PEG0 x4, Clock 0 (SSD2)
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST#
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register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
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device generic 0 on end
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end
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end
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device ref tbt_pcie_rp0 on end
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device ref gna on end
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device ref tcss_xhci on
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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device ref tcss_root_hub on
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device ref tcss_usb3_port1 on end
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end
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end
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device ref tcss_dma0 on end
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# From PCH EDS(TODO)
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device ref xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
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end
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device ref shared_sram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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# Touchpad I2C bus
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register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.desc" = ""FocalTech Touchpad""
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register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 38 on end
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end
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end
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device ref heci1 on end
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device ref sata on
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register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
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register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
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end
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device ref pcie_rp5 on
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# PCIe root port #5 x1, Clock 2 (WLAN)
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST#
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register "srcclk_pin" = "2" # WLAN_CLKREQ#
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device generic 0 on end
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end
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end
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device ref pcie_rp6 on
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# PCIe root port #6 x1, Clock 5 (CARD)
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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# XXX: No enable_gpio = no D3cold?
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST#
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register "srcclk_pin" = "5" # CARD_CLKREQ#
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device generic 0 on end
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end
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end
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device ref pcie_rp7 on
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# PCIe root port #7 x1, Clock 6 (GLAN)
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# Clock source is shared with LAN and hence marked as free running.
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 6,
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.clk_req = 6,
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.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x4, Clock 1 (SSD1)
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST#
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register "srcclk_pin" = "1" # SSD_CLKREQ#
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device generic 0 on end
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end
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end
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device ref pch_espi on
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register "gen1_dec" = "0x00040069" # EC PM channel
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register "gen2_dec" = "0x00fc0E01" # AP/EC command
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register "gen3_dec" = "0x00fc0F01" # AP/EC debug
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device ref p2sb on end
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device ref pmc hidden end
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device ref hda on
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#register "PchHdaAudioLinkHdaEnable" = "1"
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end
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device ref smbus on end
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device ref fast_spi on end
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end
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end
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