7f8b0cd89c
This patch replaces hard-coded PCI IDs with macros from pci_ids.h and cleans up some code. Change-Id: Ie6ea72ac49eb015ef5cbaa98ed2b3400072000b5 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
294 lines
8.5 KiB
C
294 lines
8.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include <types.h>
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#include "chip.h"
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#include "i82801ix.h"
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typedef struct southbridge_intel_i82801ix_config config_t;
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static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
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const int is_mobile)
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{
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int i;
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u32 reg32;
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struct resource *res;
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/* Initialize AHCI memory-mapped space */
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res = find_resource(dev, PCI_BASE_ADDRESS_5);
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if (!res)
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return;
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u8 *abar = res2mmio(res, 0, 0);
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printk(BIOS_DEBUG, "ABAR: %p\n", abar);
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/* Set AHCI access mode.
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No other ABAR registers should be accessed before this. */
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reg32 = read32(abar + 0x04);
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reg32 |= 1 << 31;
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write32(abar + 0x04, reg32);
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/* CAP (HBA Capabilities) : enable power management */
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reg32 = read32(abar + 0x00);
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/* CCCS must be set. */
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reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */
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reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
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write32(abar + 0x00, reg32);
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/* PI (Ports implemented) */
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write32(abar + 0x0c, port_map);
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/* PCH code reads back twice, do we need it, too? */
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(void) read32(abar + 0x0c); /* Read back 1 */
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(void) read32(abar + 0x0c); /* Read back 2 */
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/* VSP (Vendor Specific Register) */
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reg32 = read32(abar + 0xa0);
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reg32 &= ~0x00000001; /* clear SLPD */
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write32(abar + 0xa0, reg32);
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/* Lock R/WO bits in Port command registers. */
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for (i = 0; i < 6; ++i) {
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if (((i == 2) || (i == 3)) && is_mobile)
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continue;
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u8 *addr = abar + 0x118 + (i * 0x80);
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write32(addr, read32(addr));
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}
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}
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static void sata_program_indexed(struct device *const dev, const int is_mobile)
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{
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u32 reg32;
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pci_write_config8(dev, D31F2_SIDX, 0x18);
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reg32 = pci_read_config32(dev, D31F2_SDAT);
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reg32 &= ~((7 << 6) | (7 << 3) | (7 << 0));
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reg32 |= (3 << 3) | (3 << 0);
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pci_write_config32(dev, D31F2_SDAT, reg32);
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pci_write_config8(dev, D31F2_SIDX, 0x28);
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pci_write_config32(dev, D31F2_SDAT, 0x00cc2080);
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pci_write_config8(dev, D31F2_SIDX, 0x40);
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pci_write_config8(dev, D31F2_SDAT + 2, 0x22);
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pci_write_config8(dev, D31F2_SIDX, 0x78);
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pci_write_config8(dev, D31F2_SDAT + 2, 0x22);
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if (!is_mobile) {
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pci_write_config8(dev, D31F2_SIDX, 0x84);
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reg32 = pci_read_config32(dev, D31F2_SDAT);
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reg32 &= ~((7 << 3) | (7 << 0));
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reg32 |= (3 << 3) | (3 << 0);
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pci_write_config32(dev, D31F2_SDAT, reg32);
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}
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pci_write_config8(dev, D31F2_SIDX, 0x88);
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reg32 = pci_read_config32(dev, D31F2_SDAT);
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if (!is_mobile)
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reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8));
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reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0));
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if (!is_mobile)
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reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8);
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reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0);
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pci_write_config32(dev, D31F2_SDAT, reg32);
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pci_write_config8(dev, D31F2_SIDX, 0x8c);
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reg32 = pci_read_config32(dev, D31F2_SDAT);
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if (!is_mobile)
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reg32 &= ~((7 << 27) | (7 << 24));
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reg32 &= ~((7 << 19) | (7 << 16) | 0xffff);
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if (!is_mobile)
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reg32 |= (2 << 27) | (2 << 24);
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reg32 |= (2 << 19) | (2 << 16) | 0x00aa;
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pci_write_config32(dev, D31F2_SDAT, reg32);
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pci_write_config8(dev, D31F2_SIDX, 0x94);
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pci_write_config32(dev, D31F2_SDAT, 0x00000022);
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pci_write_config8(dev, D31F2_SIDX, 0xa0);
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reg32 = pci_read_config32(dev, D31F2_SDAT);
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reg32 &= ~((7 << 3) | (7 << 0));
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reg32 |= (3 << 3) | (3 << 0);
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pci_write_config32(dev, D31F2_SDAT, reg32);
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pci_write_config8(dev, D31F2_SIDX, 0xa8);
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reg32 = pci_read_config32(dev, D31F2_SDAT);
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reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0));
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reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0);
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pci_write_config32(dev, D31F2_SDAT, reg32);
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pci_write_config8(dev, D31F2_SIDX, 0xac);
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reg32 = pci_read_config32(dev, D31F2_SDAT);
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reg32 &= ~((7 << 19) | (7 << 16) | 0xffff);
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reg32 |= (2 << 19) | (2 << 16) | 0x000a;
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pci_write_config32(dev, D31F2_SDAT, reg32);
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}
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static void sata_init(struct device *const dev)
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{
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u16 reg16;
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/* Get the chip configuration */
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const config_t *const config = dev->chip_info;
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const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID);
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const int is_mobile = (devid == PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_IDE_P01) ||
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(devid == PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_AHCI_P0145);
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u8 sata_mode;
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printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n");
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if (config == NULL) {
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printk(BIOS_ERR, "i82801ix_sata: error: "
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"device not in devicetree.cb!\n");
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return;
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}
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if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
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/* Default to AHCI */
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sata_mode = 0;
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/*
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* TODO: In contrast to ICH7 and PCH code we don't set
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* timings, dma and IDE-I/O settings here. Looks like they
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* became obsolete with the fading of real IDE ports.
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* Maybe we can safely remove those settings from PCH code and
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* even ICH7 code if it doesn't use the feature to combine the
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* IDE and SATA controllers.
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*/
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY | /* read-only in IDE modes */
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PCI_COMMAND_IO);
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if (sata_mode != 0)
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
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if (sata_mode == 0) {
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printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
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} else {
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printk(BIOS_DEBUG, "SATA controller in native mode.\n");
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/* Enable native mode on both primary and secondary. */
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pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);
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}
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/* Looks like we should only enable decoding here. */
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pci_write_config16(dev, D31F2_IDE_TIM_PRI, (1 << 15));
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pci_write_config16(dev, D31F2_IDE_TIM_SEC, (1 << 15));
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/* Port enable. For AHCI, it's managed in memory mapped space. */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map);
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pci_write_config16(dev, 0x92, reg16);
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/* SATA clock settings */
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u32 sclkcg = 0;
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if (config->sata_clock_request &&
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!(inb(DEFAULT_GPIOBASE + 0x30) & (1 << (35 - 32))))
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sclkcg |= 1 << 30; /* Enable SATA clock request. */
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/* Disable unused ports. */
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sclkcg |= ((~config->sata_port_map) & 0x3f) << 24;
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/* Must be programmed. */
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sclkcg |= 0x193;
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pci_write_config32(dev, 0x94, sclkcg);
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if (is_mobile && config->sata_traffic_monitor) {
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struct device *const lpc_dev = pcidev_on_root(0x1f, 0);
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if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF)
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>> 3) & 3) == 3) {
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u8 reg8 = pci_read_config8(dev, 0x9c);
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reg8 &= ~(0x1f << 2);
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reg8 |= 3 << 2;
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pci_write_config8(dev, 0x9c, reg8);
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}
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}
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if (sata_mode == 0)
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sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile);
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sata_program_indexed(dev, is_mobile);
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}
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static void sata_enable(struct device *dev)
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{
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/* Get the chip configuration */
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const config_t *const config = dev->chip_info;
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u16 map = 0;
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u8 sata_mode;
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if (!config)
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return;
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if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
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/* Default to AHCI */
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sata_mode = 0;
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/*
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* Set SATA controller mode early so the resource allocator can
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* properly assign IO/Memory resources for the controller.
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*/
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if (sata_mode == 0)
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map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */
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map |= (config->sata_port_map ^ 0x3f) << 8;
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pci_write_config16(dev, 0x90, map);
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}
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static struct pci_operations sata_pci_ops = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.enable = sata_enable,
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.scan_bus = 0,
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.ops_pci = &sata_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_82801IB_SATA_P0123,
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PCI_DEVICE_ID_INTEL_82801IB_SATA_P01,
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PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI1,
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PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI2,
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PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_IDE_P01,
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PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_AHCI_P0145,
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0,
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};
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static const struct pci_driver pch_sata __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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